⚛️ Module 1 · Physics Foundation · Chapter 1.6 · 14 min read

Capacitance and the RC Time Constant

Electricity's memory — and its clock.

Prerequisites

What you'll learn here

  • Use Q = C·V and define capacitance
  • Interpret the RC time constant τ = R·C
  • Read 63% and 95% points off V_C(t) = V_in(1 − e^(−t/τ))
  • Explain CMOS dynamic power P = α·C·V²·f
  • Say why capacitors are the 'time translators' in SIDRA's TDC readout

Hook: A Capacitor Remembers

Ohm’s law defined resistance: a voltage, an instantaneous current. No time. But in real circuits time is everything — clock rate, switching loss, analog readout. The source is one component: the capacitor.

A capacitor remembers applied voltage. Charge it, remove the source, voltage doesn’t drop instantly — it lingers. That memory is everywhere on a modern chip: MOSFET gate capacitance (opening a gate takes time), wire capacitance (signal propagation), and the integration capacitor in SIDRA’s TDC that turns memristor current into time.

This chapter: τ=R⋅C\tau = R \cdot C, one formula, the whole time budget of a modern chip.

Intuition: Two Plates, One Dielectric

A capacitor = two conductive plates + an insulator (dielectric) between. If one plate takes +Q, the other mirrors −Q. Between them, an electric field and a voltage:

Q=C⋅VQ = C \cdot V

Bigger CC → same Q at lower V. Unit: Farad (F). On modern chips: femtofarad (10⁻¹⁵ F) to picofarad (10⁻¹² F).

Wire an R and a C in series. Turn on the supply; the capacitor starts to charge. Current is I=dQ/dt=C⋅dVC/dtI = dQ/dt = C \cdot dV_C/dt by definition. From Ohm, I=(Vin−VC)/RI = (V_{in} - V_C)/R. Equate:

R⋅C⋅dVCdt+VC=VinR \cdot C \cdot \frac{dV_C}{dt} + V_C = V_{in}

Solution:

VC(t)=Vin⋅(1−e−t/τ),τ=R⋅CV_C(t) = V_{in} \cdot (1 - e^{-t/\tau}), \quad \tau = R \cdot C

At t=τt = \tau the voltage reaches 63% of target. At t=5τt = 5\tau, 99%. So: τ is how fast you approach the goal.

Discharging (V_in removed): VC(t)=V0⋅e−t/τV_C(t) = V_0 \cdot e^{-t/\tau} — decay with the same τ.

Formalism: τ, Energy, Power

L1 · Intro

Three numbers:

  • τ = R·C → approach-time to target.
  • 63% @ 1τ, 99% @ 5τ. “Fully charged” ≈ 5τ in practice.
  • Small C → fast charge. Big R → slow charge. Same τ trades R ↔ C.
L2 · Full

Energy stored in a capacitor:

E=12CV2E = \frac{1}{2} C V^2

Half of this energy is dissipated in the resistor during charging — ideal source+R+C chain is 50% efficient. This is the heart of CMOS dynamic power:

Pdyn=α⋅CL⋅VDD2⋅fP_{dyn} = \alpha \cdot C_L \cdot V_{DD}^2 \cdot f
  • CLC_L: total load capacitance
  • VDDV_{DD}: supply voltage
  • ff: clock frequency
  • α\alpha: activity factor (0-1, how many gates toggle)

Every transition burns half-CV2CV^2; halving happens again next cycle. Lowering VDDV_{DD} (3.3 V → 1 V over years) is the main source of efficiency gains.

MOSFET gate capacitance:

Cox=εoxtox⋅W⋅LC_{ox} = \frac{\varepsilon_{ox}}{t_{ox}} \cdot W \cdot L

At 28 nm, EOT ∼1.2\sim 1.2 nm (with HfO₂ high-k). Each gate is ~fF; a chip has billions → totals reach pF.

L3 · Deep

Parasitic capacitance: wire-to-wire, wire-to-substrate, source-to-drain. Modern chip timing is dominated by parasitics. Interconnect RC delay has grown past transistor delay — the RC-dominated regime.

Dielectric constant: C=ε0εrA/dC = \varepsilon_0 \varepsilon_r A / d. SiO₂ has εr=3.9\varepsilon_r = 3.9. HfO₂ has ~25. Same area, same thickness → 6× more capacitance. For the gate this is good (thin EOT, low tunneling); for interconnect it’s bad (high parasitic → low-k dielectrics are sought).

SIDRA TDC readout: memristor current I=V⋅GI = V \cdot G charges an integration capacitor. When does voltage cross the threshold? tthr=C⋅Vthr/It_{thr} = C \cdot V_{thr} / I — so current is translated into time. A 6-bit TDC at 3.125 ps is 10-30× more efficient than an ADC. The capacitor’s “memory” becomes a measurement tool.

Memristor RC time: memristor + parasitic τ=Rmem⋅Cpar\tau = R_{mem} \cdot C_{par}. 100 kΩ × 1 fF = 100 ps — that’s the floor for a crossbar “read” cycle.

Experiment: Feel the τ

Steps:

  1. R = 10 kΩ, C = 1 pF → τ = 10 ns. Hit “Charge”. Curve should hit 63% at 10 ns, 99% at 50 ns.
  2. Raise R to 100 kΩ. τ grows 10×. Curve 10× slower.
  3. Make C = 10 pF. Another 10× slower.
  4. R = 1 kΩ, C = 0.1 pF → τ = 0.1 ns. Near-instant — modern high-speed logic.
  5. After full charge, press “Discharge” — exponential decay with the same τ.

Quiz

1/5Q = C·V. What's the unit of C?

Lab Task: Real Numbers

(a) 28 nm MOSFET gate area = 28 nm × 100 nm = 2800 nm². EOT 1.2 nm. SiO₂ εr=3.9\varepsilon_r = 3.9, ε0=8.854×10−12\varepsilon_0 = 8.854 \times 10^{-12} F/m. Compute gate capacitance CoxC_{ox}.

(b) Toggle this MOSFET’s gate at 1 V, 1 GHz. Energy per transition 12CV2\tfrac{1}{2}CV^2?

(c) SIDRA Y1: 16 CU × 4 layers × 1,600 subarray × 256×256 = 419M cells. If all toggle at 500 MHz (hypothetical), total PdynP_{dyn}? (C_cell = 0.5 fF, V = 0.1 V, α = 1.)

Answers

(a) C=3.9⋅8.854×10−12⋅2800×10−18/(1.2×10−9)C = 3.9 \cdot 8.854 \times 10^{-12} \cdot 2800 \times 10^{-18} / (1.2 \times 10^{-9}) ≈ 0.08 fF. Realistic ~fF range.

(b) E=0.5⋅0.08×10−15⋅1=0.04E = 0.5 \cdot 0.08 \times 10^{-15} \cdot 1 = 0.04 fJ = 40 aJ. Same order as the 10 aJ analog MVM from Chapter 1.5.

(c) P=αCV2f=1⋅0.5×10−15⋅0.01⋅5×108⋅419×106P = \alpha C V^2 f = 1 \cdot 0.5 \times 10^{-15} \cdot 0.01 \cdot 5 \times 10^8 \cdot 419 \times 10^6 ≈ 10.5 W. Real Y1 TDP is ~3 W, so average α ≪ 1 (sparse activity). This shows why α matters.

Cheat Sheet

  • Q = C·V, unit: Farad; on-chip fF-pF.
  • τ = R·C — time constant; VC(t)=Vin(1−e−t/τ)V_C(t) = V_{in}(1−e^{−t/τ}).
  • 63% @ 1τ, 95% @ 3τ, 99% @ 5τ. “Fully charged” ≈ 5τ.
  • Energy: E=12CV2E = \tfrac{1}{2}CV^2; half is lost to R during charge.
  • CMOS dynamic power: P=αCV2fP = \alpha CV^2 f. Quadratic in V.
  • MOSFET gate: Cox=ε/tox⋅W⋅LC_{ox} = \varepsilon/t_{ox} \cdot W \cdot L; ~fF at 28 nm.
  • SIDRA TDC: cap converts memristor current to time — 6-bit, 3.125 ps.

Vision: Beyond the Passive Capacitor

Advanced capacitance:

  • Ferroelectric capacitor (HZO): nonlinear C-V; retains voltage. FeFET = nonvolatile cap + gate.
  • Negative capacitance: ferroelectric overshoot yields sub-60 mV/decade — an attempt to beat Landauer.
  • Supercapacitors: on-chip energy harvest + hourly drive. Graphene electrodes reach 1 µF/mm².
  • RC-bypass photonics: Si-photonic waveguide bandwidth is independent of RC — Y100’s bet.
  • Memcapacitor: memory-carrying capacitance (memristor’s passive sibling). An alternative SIDRA analog-weight cell.
  • Quantum capacitance: density-of-states ceiling in 2D materials — critical for MOSFET subthreshold slope.
  • Liquid-metal capacitor: tunable C with Galinstan; RF front-ends and adaptive filters.
  • On-chip MEMS capacitor: mechanical position → C variation; low-noise ADC reference.

Biggest lever for post-Y10 SIDRA: a negative-capacitance gate — adding HZO to the FinFET/GAA gate cuts dynamic power αCV2f\alpha CV^2 f by 40% at the same ff. With TDP held constant, clock frequency can then rise 2×. 2026–2028 horizon.

Further Reading