MOSFET — The Atom of 28 nm CMOS

Hook: 10¹⁸ Switches a Second

Right now, in the device you’re reading this on, roughly 10¹⁸ MOSFETs are flipping every second. Each is about 28 nanometers wide — a quarter of a virus. Each is a controlled valve that turns “gate voltage” into “current”. By the end of this chapter you’ll be able to draw one.

Chapter 1.3 gave us the diode — one-way but uncontrolled. MOSFET is the same idea with a third terminal: the gate. Put a small voltage on the gate, open or close the main current path. SIDRACHIP’s 28 nm CMOS base die has billions of MOSFETs driving the memristor layers above — this chapter is how they work.

Intuition: Does the Channel Open?

Cross-section of an n-channel MOSFET:

p-type substrate (bottom, broad) — hole-heavy silicon.
n⁺ source and n⁺ drain — two heavily-doped electron pools buried in the substrate.
Gate (top, metal or polysilicon) — insulated from substrate by a thin oxide (SiO₂).

With no gate voltage, there’s no channel. Source and drain look like two back-to-back diodes; no current.

Apply a positive voltage to the gate. Electrons in the p-substrate are electrostatically pulled toward the surface under the gate. Past a threshold $V_{th}$ (typically 0.3-0.5 V) an inversion layer forms right at the surface: despite being p-substrate, electrons dominate there. That layer connects source to drain — the channel opened.

Now put a positive $V_{DS}$ on the drain and electrons flow source → drain. The channel is a voltage-controlled valve.

Formalism: Square-Law MOSFET

L1 · Intro

Three regimes:

Off ( $V_{GS} < V_{th}$ ): no channel, $I_D \approx 0$ .
Triode ( $V_{DS} < V_{GS} - V_{th}$ ): channel open and uniform; $I_D$ grows with both $V_{GS}$ and $V_{DS}$ — like a small resistor.
Saturation ( $V_{DS} \geq V_{GS} - V_{th}$ ): channel pinches off at the drain end; current depends almost only on $V_{GS}$ .

For digital switching: triode ≈ “on low-R”, saturation ≈ “on constant-current”. Below $V_{th}$ = off.

L2 · Full

Square-law MOSFET equations:

Triode:

I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_{th}) V_{DS} - \frac{V_{DS}^2}{2} \right]

Saturation:

I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})^2

Terms:

$\mu_n$ : electron mobility (Si ~400 cm²/V·s).
$C_{ox} = \varepsilon_{ox}/t_{ox}$ : gate oxide capacitance per area.
$W/L$ : channel width / length (designer’s knob — at 28 nm, $L = 28$ nm).
$V_{ov} = V_{GS} - V_{th}$ : “overdrive”.

CMOS inverter: one n-MOS + one p-MOS driven by the same input. When one is on, the other is off. Output: input 1 → output 0, input 0 → output 1. Power only during transitions (static ≈ 0). The foundation of all digital logic.

L3 · Deep

Short-channel effects below $L < 100$ nm:

V_th roll-off: shorter $L$ → drain field reaches into the source barrier (DIBL) → lower $V_{th}$ .
Subthreshold slope: $S = \ln(10) (kT/q)(1 + C_{dep}/C_{ox})$ . Theoretical floor 60 mV/decade.
Leakage: tunneling through the gate oxide — solved by high-k dielectrics like HfO₂ (yes, the same material that becomes our memristor!).
Velocity saturation: at high field, electron drift velocity saturates; $I_D$ turns linear in $V_{ov}$ instead of quadratic.

FinFET (14 nm) and GAA (3 nm): planar control fails, so the gate wraps the channel on 3 sides (FinFET) or all 4 (Gate-All-Around nanosheet).

Relevant for SIDRA: the 28 nm N28HPC+ base die uses conventional planar HKMG (High-K Metal Gate) MOSFETs. HfO₂ appears twice: as the gate dielectric and as the memristor above — same material, two roles.

Experiment: Turn the Gate, Watch the Channel

Try:

$V_{GS} = 0$ , $V_{DS} = 0.5$ : no channel. $I_D = 0$ . “OFF” chip.
Slowly raise $V_{GS}$ . At $V_{th} = 0.4$ V the channel line appears. Current still small.
$V_{GS} = 0.6$ : channel thicker; if $V_{DS} < V_{GS} - V_{th}$ → “TRIODE”.
Raise $V_{DS}$ — when $V_{DS} \geq V_{GS} - V_{th}$ the drain end pinches off, “SATURATION” appears.
$V_{GS} = 1.2$ , $V_{DS} = 1.2$ : fully saturated. Current $\propto (V_{GS} - V_{th})^2$ .

Channel thickness is drawn proportional to $(V_{GS} - V_{th})$ ; in saturation the drain-end narrowing is visible.

Quiz

1/5How does the channel form in an n-channel MOSFET?

Lab Task: I_D Calculation

Data: $\mu_n C_{ox} = 200$ µA/V², $W/L = 10$ , $V_{th} = 0.4$ V.

(a) $V_{GS} = 1.0$ V, $V_{DS} = 1.0$ V → $I_D$ ? (Hint: saturation?) (b) $V_{GS} = 1.0$ V, $V_{DS} = 0.3$ V → $I_D$ ? (Hint: triode?) (c) $V_{GS} = 0.3$ V, $V_{DS} = 1.0$ V → $I_D$ ?

Answers

(a) $V_{ov} = 0.6$ , $V_{DS} (1.0) > V_{ov} (0.6)$ → saturation. $I_D = \tfrac{1}{2}(200 \cdot 10)(0.6)^2 = 1000 \cdot 0.36 = 360$ µA.

(b) $V_{DS} (0.3) < V_{ov} (0.6)$ → triode. $I_D = (200 \cdot 10)[0.6 \cdot 0.3 − 0.3²/2] = 2000 \cdot [0.18 − 0.045] = 2000 \cdot 0.135 = 270$ µA.

(c) $V_{GS} (0.3) < V_{th} (0.4)$ → off. $I_D ≈ 0$ (real subthreshold leakage ignored here).

Cheat Sheet

MOSFET: 3-terminal — source (S), drain (D), gate (G). n-channel: S/D are n⁺, substrate is p.
Threshold $V_{th}$ ≈ 0.3-0.5 V in modern CMOS. V_GS > V_th → inversion channel.
Triode: V_DS < V_ov, linear+quadratic; digital 0.
Saturation: V_DS ≥ V_ov, pinch-off, $I_D \propto V_{ov}^2$ ; digital 1.
CMOS: NMOS + PMOS = inverter; static power ≈ 0, dynamic = C·V²·f.
SIDRACHIP: 28 nm N28HPC+ HKMG MOSFETs under the memristor stack.

Vision: Beyond Planar MOSFET

Planar MOSFET hit a physics wall at 28 nm. Next generations:

FinFET (14-7 nm): gate wraps the channel on 3 sides (Intel from 22 nm, TSMC 16 nm). Candidate for SIDRA Y10 evaluation.
Gate-All-Around (GAA) nanosheet (3-2 nm): gate wraps all 4 sides. Samsung 3 nm (2022), TSMC N2 (2025), Intel 18A.
CFET (Complementary FET): stacked NMOS + PMOS vertically; ~0.5× area.
2D MoS₂ transistor: sub-2 nm channel — IBM 2024 demo, density leap.
Neuromorphic synaptic transistor: gate capacitance carries an analog weight — 3-terminal memristor; alternate topology to SIDRA.
Spintronic logic: MTJ-based gate — infinite endurance, ferromagnetic-state logic.
TFET (Tunnel FET): band-to-band tunneling breaks the 60 mV/dec floor; ultra-low-power IoT.
Ferroelectric FET (FeFET): HZO gate → non-volatile logic + memory in one device.
Cryogenic CMOS: transistors that operate at 4 K; quantum control chips, superconducting AI hybrids.

Biggest lever for post-Y10 SIDRA: CFET plus a BEOL analog memristor layer — 2× digital-control density from CFET, plus vertically stacked memristors for MVM. Total density 4–5× vs. Y10. 2029–2031 horizon.

MOSFET — The Atom of 28 nm CMOS

Prerequisites

What you'll learn here

Hook: 10¹⁸ Switches a Second

Intuition: Does the Channel Open?

Formalism: Square-Law MOSFET

Experiment: Turn the Gate, Watch the Channel

Quiz

Lab Task: I_D Calculation

Cheat Sheet

Vision: Beyond Planar MOSFET

Further Reading

Prerequisites

What you'll learn here

🪝 Hook: 10¹⁸ Switches a Second

🧭 Intuition: Does the Channel Open?

📐 Formalism: Square-Law MOSFET

🧪 Experiment: Turn the Gate, Watch the Channel

📝 Quiz

🛠️ Lab Task: I_D Calculation

🗂️ Cheat Sheet

🔮 Vision: Beyond Planar MOSFET

📚 Further Reading

Hook: 10¹⁸ Switches a Second

Intuition: Does the Channel Open?

Formalism: Square-Law MOSFET

Experiment: Turn the Gate, Watch the Channel

Quiz

Lab Task: I_D Calculation

Cheat Sheet

Vision: Beyond Planar MOSFET

Further Reading