💻 Module 6 · Software Stack · Chapter 6.3 · 9 min read

RISC-V Firmware

The RISC-V core inside the SIDRA chip — local control flow.

Prerequisites

What you'll learn here

  • Explain the role of the embedded RISC-V core in Y1
  • Describe the firmware-driver communication protocol
  • State RISC-V ISA basics and why it's an open standard
  • Read boot sequence and calibration firmware steps
  • Summarize Y10+ firmware extensions

Hook: The Chip's Brain Is a RISC-V

Inside SIDRA Y1 there is a RISC-V core. Tasks:

  • Boot calibration (init).
  • Process driver commands (load model, start inference).
  • Error monitoring + reporting.
  • Power management commands.
  • Firmware update.

Why RISC-V? Open ISA → no licensing, strategic for Türkiye (we don’t take ARM licenses).

Intuition: Microcontroller Inside the Chip

Y1 RISC-V:

  • 32-bit RV32IM (integer + multiply).
  • 100 MHz clock.
  • 64 KB ROM (boot + recovery firmware).
  • 256 KB SRAM (runtime).
  • DMA + interrupt controller.

When the driver writes a command, RISC-V interprets it, sends instructions to the crossbars, returns results. Like a “scheduler” for the commands.

Formalism: Firmware Code

L1 · Başlangıç

Boot sequence:

void boot(void) {
    init_clock(100_000_000);
    init_dma();
    init_thermal_sensors();
    
    // Crossbar calibration
    for (int c = 0; c < N_CLUSTERS; c++)
        calibrate_cluster(c);
    
    // Driver-ready signal
    write_register(REG_STATUS, STATUS_READY);
    
    // Wait for commands
    main_loop();
}

void main_loop(void) {
    while (1) {
        wait_for_command();  // interrupt or polling
        cmd_t cmd = read_command();
        switch (cmd.type) {
            case CMD_LOAD_MODEL:
                handle_load_model(cmd);
                break;
            case CMD_INFER:
                handle_inference(cmd);
                break;
            case CMD_CALIBRATE:
                handle_calibration(cmd);
                break;
            // ...
        }
    }
}

Inference handler:

void handle_inference(cmd_t cmd) {
    // Read input vector via DMA
    read_dma(cmd.input_addr, input_buffer, cmd.input_size);
    
    // MVM commands to crossbars
    for (int layer = 0; layer < model.n_layers; layer++) {
        run_mvm(layer, input_buffer, output_buffer);
        apply_activation(layer);
        swap_buffers();
    }
    
    // Write output to DMA
    write_dma(output_buffer, cmd.output_addr, output_size);
    
    // Interrupt driver
    raise_interrupt(INT_INFERENCE_DONE);
}
L2 · Tam

RISC-V ISA basics:

RISC-V (Reduced Instruction Set Computing - Five) Berkeley 2010+. Open standard. Modular:

  • RV32I/RV64I: base integer.
  • RV32M: multiply.
  • RV32F/D: float (Y1 doesn’t need it).
  • RV32C: compressed (16-bit instructions).

Y1 RV32IM is enough. No complex math needed for crossbar control.

Typical RISC-V instructions:

addi t0, x0, 100      # t0 = 100
lw   t1, 0(s0)        # t1 = mem[s0]
sw   t0, 4(s0)        # mem[s0+4] = t0
beq  t0, t1, label    # if t0 == t1, jump

Firmware size:

64 KB ROM is sufficient (Y1):

  • Boot: 4 KB.
  • Command handlers: 20 KB.
  • Crossbar driver: 15 KB.
  • Power management: 5 KB.
  • DMA: 5 KB.
  • Recovery: 15 KB (firmware fail-safe).
L3 · Derin

Firmware update:

Firmware updates from the driver:

  1. New firmware binary uploaded to the driver.
  2. Driver IOCTL forwards to RISC-V.
  3. RISC-V writes to its own flash (with signature check).
  4. Reboot.

Security: firmware is signed (RSA-2048). Unauthorized firmware rejected.

Why RISC-V for Türkiye:

ARM license:

  • $1-10M one-time + royalty.
  • US/UK political control.

RISC-V:

  • No license.
  • Türkiye’s academic freedom.
  • BİLGEM and universities have designed RISC-V cores.

SIDRA’s RISC-V choice = strategy (away from classical licensing).

Y10+ firmware expansion:

  • Y10: RISC-V 64-bit, 200 MHz. STDP learning control.
  • Y100: RISC-V multi-core (4 cores). Complex scheduling.
  • Y1000: RISC-V + AI accelerator (firmware does its own AI).

Test and simulation:

Firmware development:

  • QEMU RISC-V emulator.
  • Verilator (RTL simulator) for chip + firmware co-simulation.
  • FPGA prototyping.

CI/CD: every commit triggers the test suite.

Codebase:

Firmware source: aether-firmware/ repo.

  • C code ~3000 lines.
  • Built with RISC-V GCC.
  • Size optimization (-Os).

Experiment: SIDRA Boot Sequence

Y1 power-on:

T = 0:    Voltage rails up (1 ms)
T = 1:    Clock stabilize (1 ms)
T = 2:    RISC-V reset deasserted
T = 2.1:  ROM boot code executes
T = 3:    DMA + interrupt init (10 ms)
T = 13:   Thermal sensor init (5 ms)
T = 18:   Crossbar calibration starts
T = 100:  Cluster 0 done
T = 200:  Cluster 1 done
...
T = 1700: All 16 clusters done
T = 1701: REG_STATUS = READY
T = 1702: Driver detects READY, sends LOAD_MODEL command
T = 2342: Model loaded (640 ms)
T = 2350: Inference ready

Total boot: ~2.4 seconds. Done once; then chip stays on.

Power-off recovery:

When power cuts:

  • RAM is lost.
  • Memristors are non-volatile → model preserved.
  • Calibration is lost → boot repeats.

Quick Quiz

1/6What architecture is Y1's firmware on?

Lab Exercise

aether-firmware test cycle.

Scenario: add a new command (CMD_THERMAL_REPORT).

Steps:

  1. In firmware/cmd.h, add CMD_THERMAL_REPORT = 10.
  2. In firmware/handlers.c, new handler:
void handle_thermal(cmd_t cmd) {
    int temp = read_thermal_sensor(cmd.cluster);
    write_response(temp);
}
  1. Build: riscv32-unknown-elf-gcc -Os -o sidra_fw.elf ....
  2. QEMU test: qemu-riscv32 -kernel sidra_fw.elf.
  3. Verilator full-chip sim.
  4. In practice: flash + reboot on a SIDRA Y1 prototype.

Time: 30 minutes (experienced developer).

Cheat Sheet

  • Y1 RISC-V: RV32IM, 100 MHz, 64 KB ROM, 256 KB SRAM.
  • Role: boot calibration + command processing + crossbar control.
  • Boot: ~2.4 seconds.
  • Update: via driver IOCTL with signature check.
  • Strategic: RISC-V open → ARM independence for Türkiye.
  • Y10+: RV64, multi-core, STDP control.

Vision: National RISC-V Ecosystem

SIDRA RISC-V firmware is part of a national ecosystem:

  • BİLGEM RISC-V cores (TÜBİTAK).
  • University research (Boğaziçi, METU, ITU).
  • ASELSAN products.

SIDRA is the largest single use in this ecosystem. Y10+ with thousands of SIDRA chips in the field → Turkish RISC-V product confidence.

Further Reading