🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.6 · 8 min read

Test and Characterization

From wafer to field chip — quality data.

Prerequisites

What you'll learn here

  • Detail the wafer/package/system test flow
  • Identify characterization measurements (DC, AC, retention, endurance)
  • Cover probe card + ATE (Automated Test Equipment)
  • Read a wafer test report
  • Explain the field-feedback yield-improvement loop

Hook: No Production Without Test

Chapter 6.9 covered the test principle (driver perspective). This chapter is the production-line view — real equipment in the workshop or mini-fab.

Key message: test at every stage, every datum recorded, continuous improvement.

Intuition: 4 Test Stages 

Wafer test (probe)
    ↓ (failed-die map)
Dicing
    ↓
Package test (final test)
    ↓ (failed packages RMA)
System test (motherboard)
    ↓ (field-ready)
Field (continuous BIST + periodic refresh)

Each stage uses different equipment + protocol.

Formalism: Test Equipment and Flow

L1 · Başlangıç

Probe-card test (wafer level):

Probe card: ~10K-pin plate. Lowered onto the wafer; touches every die.

Tests:

  • DC: VDD = 1V, IDD < 100 mA (transistor health).
  • AC: 1 GHz clock, output verification.
  • Crossbar: program + read 16 reference cells.
  • Memory: SRAM walking-bit.

Time: 30 s/die. 38-die wafer = 20 min + setup.

ATE (Automated Test Equipment): Teradyne, Advantest. SIDRA Y1: $2M equipment (basic config).

Failed-die map:

Pass/fail recorded per die. Pass dies go to packaging; fails marked (ink dot + database).

Yield: 75% → 28 good/wafer.

Package test (final test):

Packaged chip placed in an ATE handler. Broader test:

  • Full memory test.
  • Full crossbar test (program + read every cell → database).
  • Thermal stress (85°C, 1 hour).
  • AI benchmark (MNIST inference).

Time: 5 min/package. 28 packages × 5 = 140 min.

Yield: 95% → 26-27 pass.

L2 · Tam

System test:

Chip mounted on motherboard. SDK runs real workloads:

  • ResNet-18 ImageNet benchmark.
  • BERT inference.
  • 24-hour thermal monitor.
  • Power profile.

Time: 8 hours (long). So batch tests (10-50 boards in parallel).

Yield: 95% → 25 ship-ready.

Characterization:

Test = pass/fail. Characterization = detailed parameter measurement.

Sample (1-10 chips) per batch:

  • Memristor retention: 1 week @ 25°C, monitor 85°C.
  • Endurance: 1M SET/RESET cycles.
  • Temperature scan: -25°C to 85°C.
  • Voltage scan: 0.6 V to 1.2 V.

Data reported → process improvement.

Yield learning:

Analyze defect types:

  • Stuck-at-LRS: 0.3% → ALD reactor cleanliness?
  • Stuck-at-HRS: 0.5% → litho resist?
  • Read fail: 0.2% → noise.

Monthly: defect pattern → process tuning → yield rises.

Y1 target: 75% → 85% by year-end.

L3 · Derin

Türkiye test ecosystem:

ASELSAN MGEO test lab (Ankara): semiconductor test experience. Usable for SIDRA.

BİLGEM test core: military product testing.

Missing: advanced ATE equipment. No Teradyne authorized distributor in Türkiye. Imports needed.

For Y10 mini-fab: $5-10M ATE investment.

Production data:

Each wafer + die + package gets a unique ID. All test data in a central database:

  • Manufacture date.
  • Operator.
  • Process parameters.
  • Test results.

Customer RMA → ID lookup → root-cause analysis.

Yield-learning algorithm:

ML model:

features = [process_params, environmental, equipment_state, ...]
model = train(features, yield_data)
optimize(process_params, model)  # max yield

The SIDRA digital twin (chapter 6.8) carries a yield model. Continuously updated.

Y10+ automation:

  • Robot wafer handler.
  • Auto-classification (ML defect recognition).
  • Real-time yield dashboard.
  • Predictive maintenance.

Personnel productivity rises 5×.

Experiment: Typical Wafer Test Report

Wafer #2027-W042:

Overall:

  • 38 dies total.
  • Pass: 28.
  • Fail: 10 (8 stuck-LRS, 1 stuck-HRS, 1 read-fail).
  • Yield: 73.7%.

Defect map:

  • Wafer edge (ring): 6 fails (edge always worse).
  • Center: 2 fails (random).
  • Other: 2 fails.

Characterization (3 samples):

  • Cell SET energy: 8.5 ± 0.5 pJ (target 10).
  • LRS resistance: 12 kΩ ± 2 (target 10).
  • HRS retention: 10⁵ s @ 85°C (>10⁴ target).

Verdict: Pass. 28 dies to packaging.

Action: edge yield low → improve ALD uniformity.

Quick Quiz

1/6What does a probe card do?

Lab Exercise

Y1 yield improvement plan.

Current: Y1 yield 67% (wafer 75 × pkg 95 × sys 95).

2027 targets:

  • Wafer: 75% → 85%.
  • Package: 95% → 97%.
  • System: 95% → 97%.
  • Net: 67% → 80%.

Actions:

(a) ALD uniformity → edge yield rises. (b) DUV resist optimize → fewer litho defects. (c) ECC + redundant cells → flexible use (tolerate defective cells). (d) Regular test-equipment calibration.

Yield improvement = direct profit improvement. 13% yield up = 20% more output.

Cheat Sheet

  • 3 test stages: wafer (probe) → package (ATE) → system (motherboard).
  • ATE equipment: Teradyne, Advantest. $2-10M investment.
  • Characterization: detailed sample analysis per batch.
  • Yield learning: defect analysis → process improvement.
  • Y1 target: 67% → 80% yield.
  • RMA: field feedback → quality improvement.

Vision: Test Automation

  • Y1: classical test, ATE.
  • Y3: ML-predicted yield model.
  • Y10: robotic automation, real-time dashboard.
  • Y100: AI-assisted defect recognition + auto-fix.
  • Y1000: quantum sensors for molecular-level testing.

Further Reading