🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.1 · 9 min read

Cleanrooms and ISO Classes

SIDRA workshop's strict physical environment — no dust, much life.

Prerequisites

What you'll learn here

  • Name the ISO 14644 cleanroom classes and their requirements
  • Detail the SIDRA workshop (UNAM) Class 5 spec
  • Explain air filtering, pressure, temperature, humidity control
  • Identify operator protocols (gown, glove, motion)
  • State the Y10 mini-fab Class 4 targets

Hook: Dust = Chip Death

Chapter 2.9: a 0.5 µm particle covers 5 cells. For Y1’s 100 nm cells, anything above 50 nm is critical. Without a cleanroom, SIDRA is impossible.

This chapter covers the physical environment of the SIDRA workshop: ISO class, air system, operator discipline.

Intuition: Even the Air Is Disciplined

Normal room air: ~10⁹ particles per m³ (above 0.5 µm).

Cleanroom Class 5: ~3520 particles/m³ (300,000× less).

Class 4: ~352/m³.

Class 1: ~10/m³ (extreme, EUV lithography).

SIDRA workshop (UNAM): Class 5. Y10 mini-fab target: Class 4.

Formalism: ISO 14644 and Workshop Design

L1 · Başlangıç

ISO 14644-1 (2015) classes:

Class0.1 µm0.5 µm5 µmTypical use
ISO 110--EUV lithography (TSMC 5 nm)
ISO 31000--Front-end CMOS
ISO 410K352-BEOL, modern AI chip
ISO 5100K3520-SIDRA Y1 (workshop)
ISO 61M35K290Older semiconductor
ISO 710M350K2900Medical devices

SIDRA Y1 workshop (UNAM):

  • Total area: 100 m².
  • Class 5 cleanroom throughout.
  • 2 ALD reactors (HfO₂).
  • 1 DUV lithography (193 nm).
  • 1 ICP-RIE etch.
  • 1 CMP station.
  • 1 metallization (PVD Cu, sputter).
L2 · Tam

Air filtering:

HEPA (High-Efficiency Particulate Air): captures 99.97% of 0.3 µm particles. ULPA (Ultra-Low): 99.999% at 0.12 µm.

HEPA suffices for Class 5. ULPA for Class 4.

Ceiling-to-floor laminar flow (no horizontal). Operator + equipment particles carried to the floor, then vacuumed/circulated.

Pressure:

Cleanroom positive pressure vs outside (15-30 Pa). When a door opens, air flows out, dirt doesn’t come in.

Temperature + humidity:

Temperature: 21°C ± 1°C (operator comfort + device stability). Humidity: 45% ± 5% (static-electricity control).

Operator protocols:

  1. Gown room — sequence:
    • Take off shoes.
    • Bone-cap (head cover).
    • Goggles + mask.
    • Coverall (full-body bunny suit).
    • 2 layers of gloves.
    • Boots.
  2. Air shower (30 s) — blow off particles.
  3. Cleanroom entry.

A single operator emits 1 million particles/minute without a bone-cap. Full gown reduces by 99%.

L3 · Derin

Workshop investment cost:

Class 5 100 m² workshop:

  • Building + infra: $2M.
  • HEPA + air system: $500K.
  • ALD reactors (2): $1M.
  • DUV lithography: $5M (used 193 nm).
  • ICP-RIE: $300K.
  • CMP: $200K.
  • PVD: $400K.
  • Test equipment: $500K.
  • Total: ~$10M.

Using UNAM (Bilkent University) infrastructure: ~$3-5M extra for SIDRA. Government support important.

Operating cost:

  • Personnel (10 engineers + 5 technicians): $1M/year.
  • Consumables (chemicals, gases, electricity): $500K/year.
  • Maintenance: $300K/year.
  • Annual: ~$2M.

100K chips/year → ~$20/chip workshop share.

Class 4 mini-fab (Y10 target):

10× larger, 1000 m² Class 4 + 100 m² Class 3 (special steps):

  • Building: $20M.
  • Equipment: $50M (new, larger).
  • Total: $70M.

Türkiye national investment needed. ASELSAN + TÜBİTAK + university consortium.

Class 1 fab (Y100):

EUV lithography + full fab:

  • Building: $500M.
  • ASML EUV (1 system): $200M.
  • Other equipment: $1B.
  • Total: $5B+.

This scale is a strategic decision for Türkiye. Realistic post-2030.

Experiment: A Day in the UNAM Workshop

08:00 morning:

  • Operator gowns up (15 min).
  • Air shower.
  • Enter cleanroom.

08:30 - 12:00:

  • Prep wafer, ALD HfO₂ deposition (2 hours).
  • DUV lithography masking (1 hour).

12:00 - 13:00:

  • Lunch. Operator reverses the protocol (de-gown, exit).

13:00 - 17:00:

  • ICP-RIE etch (1 hour).
  • CMP planarization (1 hour).
  • PVD Cu (1 hour).
  • Test measurement (1 hour).

17:00:

  • Cleanroom exit protocol.

Daily output: 1-2 wafers (each wafer 38 dies × 2-week process).

Annual: ~3700 wafers = 100K chip capacity. Detail in chapter 7.4.

Quick Quiz

1/6ISO Class 5 cleanroom particle limit?

Lab Exercise

UNAM workshop daily production scale.

Data:

  • Workshop produces 1 wafer in 5 days (5 wafers/week).
  • Annual 50 weeks × 5 = 250 wafers/year (UNAM current capacity).
  • Per wafer 38 dies × 75% yield = 28 chips.
  • Annual: 250 × 28 = 7000 chips.

Questions:

(a) For 100K chips/year target, how many workshops? (b) Or how many wafers/week needed? (c) How much can a mini-fab (1000 m²) produce?

Solutions

(a) 100K / 7000 = 14 workshops. 14 university-style workshops in Türkiye possible, but distribution is uneconomic.

(b) 100K chips / 28 = 3570 wafers/year = 70 wafers/week = 14 wafers/day. 14× UNAM. Single-workshop expansion $50M+.

(c) Mini-fab (Class 4, 1000 m²): 100 wafers/day × 50 weeks = 35K wafers/year = 1M chips. Ideal capacity for Y10 generation.

Conclusion: UNAM workshop suffices for SIDRA Y1 small-batch. Y10 needs a mini-fab. 1-2 mini-fabs in Türkiye realistic between 2028-2030.

Cheat Sheet

  • ISO 14644-1: cleanroom standard, class = particles/m³.
  • SIDRA Y1: ISO 5, UNAM workshop.
  • Y10 mini-fab: ISO 4 target, $70M investment.
  • Y100 fab: ISO 1 + EUV, $5B+.
  • Operator protocol: gown + air shower + full gear.
  • Production: 100K chips/year Y1 workshop capacity.

Vision: Semiconductor Sovereignty in Türkiye

  • Y1 (2026): UNAM workshop, small batch.
  • Y3 (2028): UNAM 2× expansion, 200K/year.
  • Y10 (2030): Mini-fab (Ankara/Antalya), 1M/year. ASELSAN + TÜBİTAK partnership.
  • Y100 (2035): Full fab. State strategic investment. EUV if needed.
  • Y1000: multiple fabs + global export.

Further Reading