🔌 Module 5 · Chip Hardware · Chapter 5.6 · 12 min read

TDC — Time-Domain Readout

Convert current to time — the key to ADC area and energy savings.

Prerequisites

5.5 — DAC — SAR + ISPP

What you'll learn here

Explain the TDC (Time-to-Digital Converter) principle and why it's an ADC alternative
Write the current-to-time conversion math for an RC integrator + comparator
Compute Y10's TDC area/power savings vs Y1's ADC
State TDC's noise, dynamic range, and speed challenges
Show how a TDC + counter combination handles precise readout

Hook: A Smart Fix to the ADC Problem

In chapter 5.4 we saw: SIDRA Y1 die area is 25% ADC, power is 33% ADC. Very expensive. Classical ADC design isn’t optimal at this scale.

Fix: TDC (Time-to-Digital Converter). Instead of digitizing the current directly, digitize time. Measuring time is cheap (counter + clock). Measuring current is expensive (high-bit ADC).

Logic: the time to charge a capacitor to a fixed voltage = inversely proportional to the current. High current → short time. Low current → long time. A counter measures that time → the digital result.

Y10 target: replace ADC with TDC → area drops 60% + power drops 50%. This chapter covers the TDC math, circuit, and practical SIDRA design.

Intuition: Capacitor Charging Race

Classical ADC: compare current against 256 references → 8-bit digital. Fast, but big and power-hungry.

TDC alternative:

Crossbar column current flows into a capacitor.
Capacitor voltage rises linearly ( $V = I \cdot t / C$ ).
Stop when voltage crosses a threshold V_th.
Elapsed time $t = V_{th} \cdot C / I$ → inverse of current.
A counter (digital) bounded by count_max counts that time.

Practical conversion:

$C = 100$ fF, $V_{th} = 0.5$ V.
$I = 1$ µA → $t = 0.5 V \cdot 100$ fF / 1 µA = $50$ ns.
$I = 10$ µA → $t = 5$ ns. (10× current, 10× shorter.)
$I = 100$ nA → $t = 500$ ns.

Counter (1 GHz clock): one count per ns. 5-500 ns range = 5-500 counts. ~9 effective bits.

Pros:

ADC: ~25 mm² in Y1.
TDC: ~10 mm² (in Y10).
Power: 1 pJ/conv (ADC) → 0.3 pJ/conv (TDC).

Cons:

Variable time (current-dependent). Doesn’t fit a fixed-clock pipeline.
Low current = long time = slow read.
Counter limits the bit depth (10-12 bits practical).

Right for SIDRA? Yes — for classification, energy matters more than speed. Prototype in Y3, standard in Y10.

Formalism: TDC Math and Circuit

L1 · Başlangıç

Core TDC equation:

t = \frac{V_{th} \cdot C}{I}

$V_{th}$ : comparator threshold (fixed, e.g. 0.5 V).
$C$ : integrating capacitor (fixed, e.g. 100 fF).
$I$ : current measured (crossbar output).
$t$ : counter output (in clock cycles).

Current vs time:

Current	Time	Counts at 1 GHz
100 nA	500 ns	500
1 µA	50 ns	50
10 µA	5 ns	5
100 µA	0.5 ns	less than 1 (below limit)

Low current → fine resolution; high current hits limit.

Typical SIDRA column current: 1-10 µA → TDC time 5-50 ns.

Counter bit depth:

500 counts = 9 bits. For more, either grow the capacitor (slows down) or speed up the clock.

L2 · Tam

TDC schematic:

crossbar column (I_in)
    ↓
   [─── (gate)
       │
   ────┼──── ↑ V_C (capacitor voltage)
       │     |
       C   [Comparator] ── threshold V_th
       │     |
   ────┼──── ↓
       │
   (ground)
       │
   [Counter] ←── 1 GHz clock
       ↓
   digital result

Operation:

Reset: switch open, discharge capacitor.
Start: switch closed, $I_{in}$ flows into capacitor. Counter starts from 0.
Wait: $V_C$ rises linearly.
Stop: $V_C \geq V_{th}$ → comparator triggers → counter stops.
Read: counter value $t$ = inverse of current.

The counter output is a digital number. Replaces the ADC.

Speed:

Min time (max current): 1 ns.
Max time (min current): 1 µs.
Typical MVM: 10-50 ns.

ADC typical 5 ns. TDC 1-1000 ns variable. Slow but flexible.

Multi-channel:

One TDC measures one column. 256 columns = 256 TDCs? No — share:

Fast pipelining: a TDC does 100M measurements/s.
256 columns / N TDCs = sharing factor.
Y10 target: 32 TDCs/CU (4× column-share) → area down 75%.

Accuracy:

Counter resolution: 1 ns (1 GHz). For current: $\Delta I = V_{th} C / t$ → resolution improves with $t$ (slow read = more precise).

SIDRA practical: ~8 effective bits (counter 256 counts), same as Y1 ADC.

L3 · Derin

TDC + sigma-delta hybrid:

TDC alone gives 8-9 bits. For more, a sigma-delta loop:

TDC measures → coarse reading.
Estimate the residual current.
Run a second TDC on the residual.
Combine the two → 12-14 effective bits.

Y10 target: hybrid TDC, 12 bits.

Thermal effects:

Capacitor value $C(T)$ has small T dependence (~30 ppm/°C). Comparator threshold is more sensitive (~100 µV/°C).

Fix: temperature-aware calibration. Each cluster has a reference TDC; the others are corrected against it.

Clock jitter:

The counter runs from a 1 GHz clock. Clock jitter ~10 ps RMS. For 1 ns counts, that’s 1% error. Tolerable in practice.

Low-current problem:

HRS cells (1 µS @ 0.25 V → 250 nA) read very slowly (~200 ns TDC). MVM throughput drops.

Fix: raise voltage (use 0.5 V on HRS) or amplify current (TIA, chapter 5.7).

TDC vs ADC compare:

Property	ADC (Y1)	TDC (Y10)
Area	25 mm² (25% die)	10 mm² (10%)
Power	1 W	0.5 W
Speed	5 ns	5-500 ns variable
Bit depth	8	8 (12 hybrid)
Complexity	High	Moderate
Maturity	Standard	Novel (SIDRA Y10)

TDC physical basis:

TDC is essentially an integrating ADC variant. Current integration = a natural low-pass filter (noise drops). ADCs are more “instantaneous samples” → more noise.

That’s why TDC SNR is naturally a bit better (~2-3 dB).

Modern uses:

IBM Telum (2021): TDC-based analog compute-in-memory tests.
Mythic AI: ADC-based (didn’t switch to TDC).
Loihi 2: digital, no TDC.
SIDRA Y10: the first major academic-research-meets-product hybrid TDC use.

Experiment: TDC Worked Example

Crossbar column MVM output: I = 5 µA.

TDC parameters: C = 100 fF, V_th = 0.5 V, counter 1 GHz.

Step 1: reset, $V_C = 0$ .

Step 2: current integration begins. $V_C(t) = I \cdot t / C = 5 \times 10^{-6} \cdot t / 10^{-13} = 5 \times 10^7 \cdot t$ V (t in seconds).

Step 3: $V_C = V_{th}$ : $5 \times 10^7 \cdot t = 0.5$ $t = 10^{-8}$ s = 10 ns.

Step 4: counter reads 10.

Counter back to current: $I = V_{th} \cdot C / t = 0.5 \cdot 10^{-13} / 10^{-8} = 5 \times 10^{-6}$ A = 5 µA. Correct.

Different currents:

I	t	Count
100 nA	500 ns	500
500 nA	100 ns	100
1 µA	50 ns	50
5 µA	10 ns	10
10 µA	5 ns	5
50 µA	1 ns	1

Counts 1-500 → ~9 effective bits. Lower current = higher precision.

Limit: above 50 µA, counts < 1 → TDC fails. Fix: bigger capacitor, or scale-down current.

Y10 SIDRA typical:

Average current 5 µA → 10 ns measurement.
256 columns, 32 shared TDCs → each measures 8 columns = 80 ns.
ADC alternative: 5 ns × 256 columns (parallel ADC) = 5 ns.

Shared TDC is 16× slower but 16× fewer TDCs → area + power savings dominate.

Quick Quiz

1/6Core TDC principle?

Lab Exercise

Y10 TDC design optimization.

Y10 specs:

1024×1024 crossbar (4× Y1).
1 cluster = 16 CU × 16 crossbars.
Target: ADC area 25% → 10%.

TDC parameters:

C = 200 fF (for dynamic range).
V_th = 0.5 V.
Clock = 2 GHz (Y10 increase).

Questions:

(a) For C = 200 fF and a typical 5 µA current, TDC time? (b) For 1024 columns with 32 TDCs (32-column share), MVM time? (c) Y1 ADC area 25 mm² → Y10 TDC area estimate? (d) TDC energy savings vs ADC? (e) Y10 total ADC+TDC area savings?

Solutions

(a) $t = V_{th} \cdot C / I = 0.5 \cdot 2 \times 10^{-13} / 5 \times 10^{-6} = 2 \times 10^{-8}$ s = 20 ns.

(b) Shared: 32 TDCs × 32 columns = 1024. Each TDC sequentially reads 32 columns → 32 × 20 ns = 640 ns/MVM. 128× slower than Y1’s 5 ns! But:

Y10 has 4× more parallel clusters.
Fewer TDCs → more crossbars run in parallel.
Net throughput: same 30 TOPS → 300 TOPS at Y10.

(c) Y10 = 4× crossbars (vs Y1). At constant ADC area: 100 mm². With TDC at 25% → ~25 mm². Y10 TDC = 25 mm² target (10% of die in a 1 cm² die).

(d) TDC: 0.3 pJ/conv. ADC: 1 pJ/conv. 3× less energy. 1024 cols × 50M conv/s × 0.3 pJ = 15 W → shared 32 TDC: 15 / 32 = 0.5 W TDC share. ADC alternative 1.5 W. 1 W saved.

(e) Total Y10 (4× Y1 crossbars): ADC est. 100 mm² → with TDC 30 mm² (70% saving). The freed area goes to compute engine + memory → real Y10 value.

Cheat Sheet

TDC: current → capacitor charge time → counter → digital. ADC alternative.
Equation: $t = V_{th} \cdot C / I$ . Inverse of current.
Y1: uses ADC (25% area, 33% power).
Y10 target: TDC saves 60% area + 50% power.
Bit depth: ~9 single-stage; 12-14 hybrid.
Time: current-dependent, 1 ns - 1 µs (5-50 ns typical).
Sharing: one TDC per 8-32 columns (area savings).
Advantage: natural integration → SNR ~2-3 dB better.

Vision: The Spread of Time-Domain Computing

TDC isn’t only for readout — entire compute can be time-domain:

Y1 (today): ADC; TDC is research.
Y3 (2027): TDC prototype in CUs (1-2 clusters).
Y10 (2029): TDC standard. Sigma-delta hybrid for 12-bit.
Y100 (2031+): Whole signal chain time-domain — DAC, MVM, ADC, all time-encoded. Spike-based.
Y1000 (long horizon): Optical time-domain (photonic pulses). Single-photon precision.

Meaning for Türkiye: time-domain analog circuit design is a strong academic research focus. SIDRA’s Y10 prototype using TDC is a return on Türkiye’s research investment — patentable, publishable, productizable.

Unexpected: astrophysics tie-in. Photomultipliers (photon detectors) already use TDCs (to time single photons). SIDRA’s TDC design draws from that tradition. Türkiye’s observatory experience (TÜBİTAK National Observatory) can flow into neuromorphic.

Prerequisites

What you'll learn here

🪝 Hook: A Smart Fix to the ADC Problem

🧭 Intuition: Capacitor Charging Race

📐 Formalism: TDC Math and Circuit

🧪 Experiment: TDC Worked Example

📝 Quick Quiz

🛠️ Lab Exercise

🗂️ Cheat Sheet

🔮 Vision: The Spread of Time-Domain Computing

📚 Further Reading