Test, Calibration, Verification

Wafer test (probe card):

Probe needles touch each die on the wafer. Tests:

• DC tests: voltage/current limits.
• Memory test: SRAM bit-by-bit.
• Crossbar test: program + read 16 reference cells.
• Interconnect test: BAR mapping.

Time: 30 s/die. 38 dies/wafer = 20 minutes.

Failed dies marked, not packaged.

Package test:

Packaged chip:

• PCIe enumeration (BIOS sees it).
• Full memory test (DDR/SRAM).
• Full crossbar test (program + read every cell).
• Thermal stress (85°C for 1 hour).

Failed chip RMA → returned to supplier.

System test:

Chip on motherboard:

• Full SDK runs.
• MNIST + ResNet inference accuracy.
• 24-hour stress test.

Pass = “accepted”, ships to customer.

Boot-time calibration:

Every chip power-up:

1. Voltage rails stabilize.
2. Thermal sensors active.
3. Bandgap reference calibrated.
4. Each crossbar reads 16 reference cells → DAC scale set.
5. Failure map loaded (from NVRAM).
6. SRAM init.
7. Driver READY signal.

Time: ~100 ms (detail in chapter 6.3).

BIST (Built-In Self-Test):

Test circuitry inside the chip. Runs automatically at boot:

void bist_run(void) {
    // SRAM walking-bit test
    for (int addr = 0; addr < SRAM_SIZE; addr++) {
        for (int bit = 0; bit < 32; bit++) {
            sram[addr] = (1 << bit);
            assert(sram[addr] == (1 << bit));
        }
    }
    
    // Crossbar reference test
    for (int xb = 0; xb < N_CROSSBARS; xb++) {
        program_reference(xb);
        if (!verify_reference(xb)) {
            mark_crossbar_bad(xb);
        }
    }
    
    // Compute engine test
    for (int op = 0; op < N_OPS; op++) {
        result = run_op(op, test_input);
        assert(result == expected[op]);
    }
}

Faulty component → update failure map, ECC routes around.

Periodic runtime test:

During inference, 1% reference MVMs. If results drift, recalibrate.

if (inference_count % 100 == 0) {
    actual = run_reference_mvm();
    if (abs(actual - expected) > THRESHOLD) {
        recalibrate_all();
    }
}

Drift, temperature changes get auto-corrected.

Failure-mode analysis:

Most failures are caught in production. Remaining are field issues:

MTBF (Mean Time Between Failures) target: 100,000 hours = 11 years.

RMA process:

Customer reports a fault → ticket → SIDRA sales → spare chip shipped → faulty returned → analyzed → supply chain improvement.

Field data → production improvement. Closed loop.

AI accuracy verification:

After deploying a compiled model on real SIDRA:

test_acc = chip.benchmark(test_data)
sim_acc = simulator.benchmark(test_data)

if abs(test_acc - sim_acc) > 0.01:
    # Sim vs chip differ by > 1%
    investigate()
    update_simulator_model()

Field data feeds the simulator. The sim model stays close to reality.

Compliance + certification:

SIDRA chip certifications:

• CE (Europe).
• FCC (US).
• TSE (Türkiye).
• AEC-Q100 (automotive for Y10+).
• DO-254 (avionics for Y100+).

Each cert requires testing + documentation + independent audit.

Production-error benchmarks:

Y1 targets:

• Wafer yield: 75%.
• Package yield: 95%.
• System yield: 95%.
• Net: 67%. Industry typical (TSMC 28 nm, ~75-85%).

Y10+ tighter, target 80% net.