Metal Lines and IR Drop

WL geometry (Y1):

• Cu, 30 nm × 50 nm × 26 µm.
• $\rho_{Cu, eff}$ = 3.5 µΩ·cm.
• $R_{\text{wire}} = \rho L / A = 3.5 \cdot 10^{-6} \cdot 2.6 \cdot 10^{-3} / 1.5 \cdot 10^{-11} = 607$ Ω.

Cell currents (worst case):

256 cells × 0.25 V × 100 µS = ~6.4 mA total (LRS cells).

In practice: 30% activity → 2 mA average.

Current distribution along WL:

The first cell taps the WL near the source → its current is the entire wire current. The last cell → only its own current.

Current decreases along WL: $I_{\text{wire}}(x) = I_{\text{total}} \cdot (1 - x/L)$

$x$: position along WL, $L$: WL length.

Voltage profile:

$V(x) = V_0 - \int_0^x I_{\text{wire}}(x') \rho/A \, dx'$ $= V_0 - I_{\text{total}} \cdot R_{\text{wire}} \cdot (x/L - x²/(2L²))$

End ($x = L$): $V(L) = V_0 - I R_{\text{wire}} / 2$.

So the effective drop is half the total (because of the falling current distribution).

Numbers:

$I_{\text{total}} = 2$ mA (avg), $R_{\text{wire}} = 600$ Ω → total IR = 1.2 V?! Way too much!

Hmm — at 600 Ω with 2 mA you’d get 1.2 V. That swallows the whole WL.

Fix: WLs are voltage-driven (held flat). Practically WL acts more like a “voltage rail”; each cell pulls current via BL.

Even so, WL drop is 50-100 mV in practice (depends on current distribution).

IR drop on BL:

BL currents accumulate (Kirchhoff). The ADC at the BL bottom sees all 256 cell currents. The cell at the top of the BL has all current flow through → highest IR drop here.

BL has the same geometry as WL = 600 Ω. Total current 256 × 12.5 µA = 3.2 mA.

Average BL drop: $3.2 mA \cdot 600 / 2 = 1$ V! Also impossible. Real design: BL is wider (50 nm × 100 nm) → R drops to ~300 Ω. Drop 0.5 V → still big.

Practical: ADC input impedance is high (kΩ) → current limited. The voltage drops less because current is bounded.

Net effect: ~5-10% MVM error.

Double-ended drive:

Drive WL from both ends. Current flows from each end → each cell takes half through the wire.

Effective drop: half. 5% → 2.5%.

Y1 standard: double-ended WL drive.

Wider wire:

Thicker WL → lower resistance. 100 nm × 100 nm WL → R = 150 Ω (4× lower). But: more area, more capacitance (RC may worsen).

Compensation:

Compiler “pre-distorts” weights: program end-cell weights slightly larger → IR drop compensated.

The Y1 simulator (chapter 6.8) includes an IR-drop model used by the compiler.

IR drop simulation (Y1):

256-cell WL, 50% sparsity:

• Active cells: 128.
• Average current/cell: 5 µA.
• Total current: 640 µA.
• WL R = 600 Ω.
• Single-end drive: drop = 640 µA × 300 Ω (half-length avg) = 192 mV. Way too big (75% of V_in).
• Double-end drive: drop = 96 mV (~40%).

Practical: BL-end ADC output is already compensated by the compiler.

Better: the compiler reads different columns at different times to thin out current. Sequential column activation.

Practical Y1 IR drop: ~5-7% sustainable. After compiler compensation, MVM error 2-3%. AI tolerates.

Y10 improvements:

• 1S1R 3D-stack: shorter WL.
• 7 nm CMOS: tighter wire + narrower lower layers.
• New wire material: Co (cobalt) instead of Cu, better (chapter 2.8).
• Target: 2% IR drop.

Y100:

• Photonic on-chip: optical signals don’t have IR drop!
• Wafer-scale: limited single-wire length.
• Target: negligible.

Voltage-regulator IR drop:

Power delivery from the VR to the crossbar (PDN). Separate problem. Decoupling caps + thick metal layers (M16-M20).

Y1 PDN IR drop: ~50 mV (5% of 1 V supply). Tolerable.

Frequency interaction:

High frequency (1 GHz) → more switching → more instantaneous current → IR spikes. Decoupling caps critical.

In low DVFS modes IR is smaller (less current).