🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.3 · 8 min read

TSMC 28nm MPW Process

SIDRA's outsourcing to Taiwan — shared-wafer economics.

Prerequisites

What you'll learn here

  • Explain the MPW (Multi-Project Wafer) concept and why it's cheap
  • State the TSMC 28 nm process and why it's SIDRA's choice
  • Understand the tape-out process and GDS-II format
  • Detail cost, schedule, IP ownership
  • Describe the challenges of a domestic (Türkiye) alternative

Hook: Wafer Sharing = Economics

A dedicated TSMC 28 nm wafer: $5000-10000. Impossible for SIDRA at the start.

MPW (Multi-Project Wafer): several customers share a single wafer. SIDRA uses ~10 cm² → ~$500-1000.

This chapter details SIDRA’s collaboration with TSMC.

Intuition: A Shared Bus

Reticule (mask area): 26 mm × 33 mm = 858 mm². Multiple customer designs fit in one reticule:

  • Customer A: 100 mm² (large SoC).
  • SIDRA: 100 mm² (Y1).
  • Customer B: 200 mm².
  • Customer C: 50 mm².
  • … total 858 mm².

One wafer 38 reticules → 38 copies per customer = shared cost.

Formalism: TSMC 28 nm Process

L1 · Başlangıç

TSMC 28 nm spec:

  • Operating voltage: 1.0 V (nominal), 0.6-1.2 V (DVFS).
  • Clock rate: ~1-2 GHz.
  • Transistor density: ~2 million/mm².
  • Metals: 8-10 layers Cu BEOL.

What SIDRA Y1 uses:

  • Substrate (Si).
  • Transistors (MOSFETs for the 1T1R cell).
  • M1-M2 metal (local control).
  • M3-M5 (compute engine + I/O).

What SIDRA adds at UNAM:

  • M3-M20 upper metal layers.
  • HfO₂ memristor BEOL.
  • Pad opening.

MPW flow:

  1. SIDRA tape-out (GDS-II).
  2. TSMC mask shop produces masks (1 month).
  3. Wafer fab runs (4 weeks).
  4. SIDRA receives bare-CMOS wafer.

Total: tape-out → wafer ~6 weeks.

MPW shuttles:

TSMC runs 4-6 shuttles/year (every 2-3 months). SIDRA aligns with this schedule.

L2 · Tam

Tape-out details:

GDS-II (Graphic Design System II) format. Polygons per metal layer.

SIDRA tape-out size: ~50 GB. Compressed hierarchically (cell-based).

DRC (Design Rule Check):

  • Minimum metal width.
  • Minimum spacing.
  • Antenna effect.
  • Densities.

DRC clean → tape-out accepted.

LVS (Layout vs Schematic): layout consistent with schematic check.

IP ownership:

SIDRA tape-out → owned by SIDRA. TSMC produces; no royalty.

If SIDRA uses TSMC IP (e.g. SerDes PHY) → license + royalty.

For Y1, TSMC standard cell library + memory generator. Licenses included in the product fee.

Cost:

ItemSingle wafer (dedicated)MPW
Mask set$1M$50K (shared)
Wafer production$5K$1K (area share)
Test$5K$5K (each customer separate)
Total (1st wafer)$1.01M$56K
Subsequent wafers$5K$1K

First SIDRA Y1 prototype via MPW ~$60K. Volume up: dedicated more economical (>1000 wafers/year).

L3 · Derin

Schedule:

TSMC MPW calendar:

  • Feb 1: tape-out deadline.
  • Mar 1: masks ready.
  • Apr 1: wafer fab begins.
  • May 1: wafer done.
  • May 15: delivered to UNAM.

Late tape-out → next shuttle (2-3 month delay).

TSMC alternative foundries:

  • Samsung 28 nm: similar price, schedule.
  • GlobalFoundries 28 nm: slightly more expensive.
  • SMIC 28 nm (China): cheap but US export controls.
  • UMC 28 nm: expensive, less capacity.

SIDRA chose TSMC: yield + MPW reputation + ecosystem.

Domestic Türkiye foundry?

No 28 nm CMOS foundry in Türkiye. Closest:

  • ASELSAN MGEO 250 nm (military).
  • BİLGEM 130 nm prototype lab.

Even 180 nm doesn’t exist in Türkiye. 28 nm production is 5-10 years away. Until Y100, SIDRA is TSMC-dependent.

IP risk:

Tape-out in TSMC’s hands → security concern. Reverse-engineerable?

Solution: critical IP (memristor know-how) stays at UNAM (BEOL). TSMC only sees commodity CMOS.

Y1 economic decision:

Annual 3700 wafers × 1000=1000 = 3.7M wafer cost. About 30% of SIDRA total production.

Y10 1M wafers/year = 1B(dedicatedwaferat1M×1B (dedicated wafer at 1M × 5000 = $5B).

Critical transition: at Y10 volumes, dedicated wafers make sense. Move off MPW.

Experiment: SIDRA Y1 First MPW

Schedule: February 2026 tape-out.

Steps:

  • Dec 2025: Tape-out prep (DRC, LVS final).
  • Jan 2026: Pre-tape-out review.
  • Feb 2026: TSMC submission.
  • Mar 2026: Masks ready.
  • Apr 2026: Wafer fab.
  • May 2026: 5 wafers arrive at SIDRA (MPW shuttle).
  • Jun 2026: UNAM BEOL.
  • Jul 2026: Test, packaging.
  • Aug 2026: First SIDRA Y1 prototype product.

First batch cost:

  • MPW tape-out: $50K (shared mask).
  • 5 wafers: $5K.
  • First run total: 55K→5×28=140prototypechips= 55K → 5 × 28 = 140 prototype chips = ~400/chip.

Production phase (2027):

  • 30 MPW shuttles/year (every 2 months, 5 wafers each).
  • 150 wafers/year × 28 = 4200 chips.
  • Y1 target 100K → 24× growth. Dedicated wafers + UNAM 14× expansion.

Quick Quiz

1/6What is MPW?

Lab Exercise

SIDRA Y1 economics: MPW vs dedicated.

(a) MPW: 56Kmask+56K mask + 1K/wafer. 100 wafers → 156K.Perchip=156K. Per chip = 156K / 2800 = $56.

(b) Dedicated: 1Mmask(once)+1M mask (once) + 5K/wafer. 100 wafers → 1.5M.Perchip=∗∗1.5M. Per chip = **535**.

(c) MPW wins at low volume. Crossover?

(d) Dedicated advantage: 1Mmaskamortizes.1000wafers→1M mask amortizes. 1000 wafers → 1M + 5M=5M = 6M / 28K = **214/chip∗∗.MPW214/chip**. MPW 56 still cheaper.

(e) 10K wafers dedicated: 1M+1M + 50M = 51M/280K=∗∗51M / 280K = **182/chip**. MPW $56 still cheaper.

Conclusion: is MPW always cheaper? No. Dedicated wafers let you use more area per wafer (cheaper silicon per chip). For 100K+ chips, dedicated is preferred.

Cheat Sheet

  • MPW: multi-customer shared wafer. Mask 50K/customer,wafer50K/customer, wafer 1K.
  • TSMC 28 nm: CMOS substrate for SIDRA.
  • Tape-out: GDS-II, DRC + LVS.
  • Schedule: tape-out → wafer 6 weeks.
  • No 28 nm foundry in Türkiye.
  • Y10+: dedicated wafer economics.

Vision: Domestic Foundry in Türkiye

  • Y1: TSMC-dependent.
  • Y3: ASELSAN/BİLGEM 130 nm sub-component domestic.
  • Y10: TÜBİTAK 90 nm pilot foundry stand-up.
  • Y100: 28 nm fab in Türkiye (political decision).
  • Y1000: EUV-equivalent → multi-fab.

Further Reading