⚛️ Module 1 · Physics Foundation · Chapter 1.9 · 12 min read

Thermodynamics and Joule Heating

Why the chip burns — and why it must not.

Prerequisites

What you'll learn here

  • Apply Joule's law P = I·V = I²R = V²/G
  • Compute temperature rise using thermal resistance R_th
  • Explain throttling and TDP; why 85°C is a critical threshold
  • Justify SIDRA Y1/Y10/Y100 cooling strategies

Hook: Every Bit, a Little Atomic Burn

Landauer, 1961: there is a thermodynamic floor to erasing one bit of information — kTln⁡2≈3×10−21kT \ln 2 \approx 3 \times 10^{-21} J at room temperature. A billion erases per second: 10⁻¹¹ W. Nothing.

Reality: a 32-bit FMAC on a modern chip burns ~3 pJ — 10⁶ × Landauer. Everything above the floor becomes heat. 3 pJ × 10¹² ops/s = 3 W. A bare piece of silicon radiates like a small lamp. Without cooling, it reaches 200°C in a second and melts.

This chapter: why chips don’t burn — and why SIDRA Y100 needs water cooling.

Intuition: Electrical Energy → Heat

Recall Ohm: a current through a resistor dissipates energy. That energy turns into heat. That’s Joule’s law:

P=I⋅V=I2R=V2RP = I \cdot V = I^2 R = \frac{V^2}{R}

Physically: flowing electrons collide, vibrate, kick the lattice. Electron energy → phonon energy → temperature.

Two sources in a chip:

  • Dynamic power (P=αCV2fP = \alpha CV^2 f, Chapter 1.6) — every switching event dissipates CV2/2CV^2/2.
  • Static power (leakage) — a “closed” transistor still leaks (VDD⋅IleakV_{DD} \cdot I_{leak}).

That power must flow out somewhere. If it doesn’t, temperature rises. Once it rises:

  1. VthV_{th} drops → leakage up → more power → hotter (thermal runaway).
  2. Thermal expansion → mechanical stress; packaging cracks.
  3. Ion migration accelerates → memristor retention falls, endurance shortens.

Critical thresholds:

  • 85°C: throttling begins (frequency scaled down).
  • 105°C: safe limit; above this, damage.
  • 150°C: silicon’s active crystal structure starts to break down.

Formalism: Ohm's Law for Heat Flow

L1 · Intro

Heat flows like electricity. Same-shape equations:

  • Electrical: V=IRV = IR
  • Thermal: ΔT=P⋅Rth\Delta T = P \cdot R_{th}

RthR_{th} = thermal resistance (K/W). Lower → heat escapes easily → cooler chip.

Typical numbers:

  • Passive (small IHS): 15-20 K/W. At 3 W → +45-60°C (Y1).
  • Heatsink + vapor chamber: 1-3 K/W. At 35 W → +35-105°C (Y10).
  • Microfluidic: 0.2-0.5 K/W. At 100 W → +20-50°C (Y100).

If you can’t lower P, you must lower RthR_{th}.

L2 · Full

Fourier’s law (thermal conduction):

q=−κ∇Tq = -\kappa \nabla T
  • qq: heat-flux density (W/m²)
  • κ\kappa: thermal conductivity — Si: 150, HfO₂: 1.5, Cu: 400 W/m·K
  • ∇T\nabla T: temperature gradient

1-D steady state: P=κAΔT/LP = \kappa A \Delta T / L. Rth=L/(κA)R_{th} = L/(\kappa A).

Thermal capacitance: the chip doesn’t heat instantly. CthC_{th} (J/K) sets how much energy it stores. Time constant τth=Cth⋅Rth\tau_{th} = C_{th} \cdot R_{th}. A silicon die: ~1 ms — sudden load spikes heat it within 1 ms.

Throttling control: on-die sensors detect >85°C and drop the clock frequency. Since P∝fP \propto f, power drops, equilibrium settles around ~90°C. SIDRA’s DVFS (Dynamic Voltage-Frequency Scaling) enforces TDP.

TDP (Thermal Design Power): what the chip can dissipate continuously. Y1 = 3 W, Y10 = 35 W, Y100 = 100 W. It’s the ceiling of sustainable performance.

L3 · Deep

Kirchhoff thermal network: thermal resistors in series add.

Rth,total=Rth,jc+Rth,cs+Rth,saR_{th,total} = R_{th,jc} + R_{th,cs} + R_{th,sa}

Each interface needs TIM (thermal interface material); otherwise air gaps trap heat.

BEOL heat problem: memristor layers conduct heat ~100× worse than silicon. Heat can’t escape upward. Y100 puts copper microchannels with water flowing every 10 layers — bringing the cooling boundary inside the stack. This is SIDRA’s distinctive thermal trick.

Thermomechanical stress: Si vs HfO₂ thermal expansion coefficients (2.6 vs 5.3 × 10⁻⁶ /K). Over 100°C swing, a 5 nm HfO₂ layer strains ~0.15 pm — cumulative fatigue and cracking.

Self-heating in memristors: 10 µA through one memristor ≈ 10⁻⁶ W/cell. All 419M active → 400 W. In practice under 1% simultaneously active → ~4 W. But local filament temperature can rise locally by ~100°C → retention suffers.

Experiment: Pick a Cooling, Watch the Temperature

Try:

  1. Passive, P = 3 W: Y1 scenario — ~80°C, below threshold, OK.
  2. Passive, P = 10 W: temperature hits 200°C — danger! Passive is not enough.
  3. Heatsink, P = 35 W: Y10 scenario — ~95°C, at throttle edge.
  4. Heatsink, P = 100 W: can’t dissipate, 225°C — Y100 infeasible with heatsink.
  5. Microfluidic, P = 100 W: Y100 scenario — ~65°C, comfortable operation.

Quiz

1/5Which is Joule's law?

Lab Task

Y10 chip: P = 35 W, ambient 25°C.

(a) For Tchip≤85°CT_{chip} \leq 85°C, maximum allowed RthR_{th}? (b) Given Rth,jcR_{th,jc} = 0.3 K/W and Case-to-sink = 0.2 K/W, how much is left for sink-to-air? (c) If P rises to 70 W with the same R_th, new temperature?

Answers

(a) ΔT=60\Delta T = 60 K. Rth,max=60/35≈1.71R_{th,max} = 60/35 \approx 1.71 K/W.

(b) Rsink−air≤1.71−0.3−0.2=1.21R_{sink-air} \leq 1.71 - 0.3 - 0.2 = 1.21 K/W. Vapor chamber + fin territory.

(c) ΔT=70⋅1.71=120\Delta T = 70 \cdot 1.71 = 120 K → 145°C. Throttling certain; likely damage. 2× P → 2× ΔT.

Cheat Sheet

  • Joule: P=I2R=V2/R=IVP = I^2 R = V^2/R = IV. Resistive losses become heat.
  • Thermal Ohm: ΔT=P⋅Rth\Delta T = P \cdot R_{th} (K/W).
  • Fourier: q=−κ∇Tq = -\kappa \nabla T; Si 150, HfO₂ 1.5, Cu 400 W/m·K.
  • Throttle @ 85°C: DVFS drops f → P → ΔT until equilibrium.
  • TDP: Y1 3 W, Y10 35 W, Y100 100 W. Performance ceiling.
  • Cooling ladder: passive (Y1, R_th~18) → heatsink (Y10, ~2) → microfluidic (Y100, ~0.5).
  • Memristor retention: T ↑ → retention falls exponentially (Arrhenius).

Vision: Beyond Conventional Cooling

Future thermal solutions:

  • Immersion cooling: dunk the chip in dielectric fluid (3M Fluorinert or mineral oil). Spreading in datacenter GPUs (2024+).
  • Peltier / thermoelectric: on-die Peltier to target hotspots. Research; efficiency ~15%.
  • Cryogenic chips: 77 K (liquid N₂) or 4 K (helium). SRAM-based AI accelerators being evaluated (quantum interface).
  • Reversible computing: trying to go below Landauer’s limit. Compute without bit-erase; Frank 2017 prototype. 100× energy reduction potential.
  • Radiative cooling: micro-metamaterial surface radiates heat through the 8-13 µm sky window. Packaging innovation.
  • 2D thermal interface: BN, graphene boost heat transfer — lower R_th.
  • Energy harvesting: Seebeck recovery of chip heat — practical for small IoT.
  • Microfluidic cooling: 50 µm channels etched into the chip with liquid flow; reaches kW/cm² densities.
  • Phase-change (PCM) heat storage: paraffin latent heat smooths transient load peaks.

Biggest lever for post-Y10 SIDRA: microfluidic cooling on 3D stacks — a 16-layer crossbar with a cooling channel every 2 layers. Thermal resistance down 3×, density up 2× while TDP stays flat. Single-phase water baseline, two-phase Fluorinert higher. 2028–2030 horizon.

Further Reading