⚛️ Module 1 · Physics Foundation · Chapter 1.7 · 13 min read

Quantum Tunneling

Electrons passing through walls — the memristor's secret.

Prerequisites

What you'll learn here

  • Estimate barrier transmission T ≈ exp(−2κd)
  • State tunneling's exponential dependence on barrier width and height
  • Connect resistive switching in HfO₂ to tunneling
  • Explain MOSFET gate leakage and Zener breakdown in tunneling terms

Hook: The Electron Through the Wall

Classical physics: if you lack the energy, you can’t cross the wall. An electron, facing an insulating barrier, stops and bounces back. In 1927 quantum mechanics added: sometimes it crosses. The probability drops exponentially with the barrier’s width and height. A single angstrom difference changes the current by a million.

This oddity shapes modern electronics:

  • MOSFET gate leakage — tunneling even through 1.2 nm oxide. Solution: HfO₂ high-k.
  • Zener diode — the reverse bias thins the barrier, electrons tunnel, giving a clamp voltage.
  • Flash memory — deliberate tunneling pumps electrons onto a floating gate.
  • SIDRA HfO₂ memristor — an oxygen-vacancy filament opens a tunneling path; conductance tracks the filament.

Intuition: A Wave Hitting the Barrier

The electron is not only a particle — it is also a wave. Against an insulating barrier, the wave doesn’t reflect fully: inside the barrier it decays exponentially. If the barrier is thin, a tiny tail leaks out the other side and resumes. Transmission probability is the square of that leaked amplitude.

The formula in one sentence: Halve the insulator thickness, and leakage doesn’t double or quadruple — it grows by a million. Few things in chip design are this exponentially sensitive.

Formalism: T ≈ exp(−2κd)

L1 · Intro

Transmission:

T≈e−2κdT \approx e^{-2\kappa d}
  • dd: barrier thickness.
  • κ=2m(V0−E)/ℏ\kappa = \sqrt{2m(V_0 - E)}/\hbar: taller barrier ⇒ larger κ.

Two rules:

  • Halve dd → TT is squared (1e-10 → 1e-5).
  • Double V0V_0 → κ\kappa rises by 2\sqrt{2}; exponent amplifies the drop.
L2 · Full

Rectangular barrier (exact):

T=[1+V02sinh⁡2(κd)4E(V0−E)]−1,κ=2m(V0−E)ℏT = \left[1 + \frac{V_0^2 \sinh^2(\kappa d)}{4E(V_0 - E)}\right]^{-1}, \quad \kappa = \frac{\sqrt{2m(V_0 - E)}}{\hbar}

Large-κd\kappa d limit:

T≈16E(V0−E)V02e−2κdT \approx \frac{16 E(V_0 - E)}{V_0^2} e^{-2\kappa d}

Numerical example: SiO₂ barrier, V0−E=3.1V_0 - E = 3.1 eV, d=1.2d = 1.2 nm. κ≈9.0×109\kappa \approx 9.0 \times 10^9 m⁻¹. 2κd≈21.62\kappa d \approx 21.6 → e−21.6≈4×10−10e^{-21.6} \approx 4 \times 10^{-10}. That translates to the gate-leakage current density.

HfO₂ win: dielectric constant ε_r ≈ 25 (SiO₂: 3.9). Same capacitance at 6× thicker film. More than double the dd → exponential suppression of tunneling, 10³-10⁴× less leakage. This is why 28 nm HKMG uses HfO₂.

L3 · Deep

Fowler-Nordheim (FN) tunneling: under strong field, the barrier turns triangular. Current density:

JFN=AE2exp⁡(−B/E)J_{FN} = A E^2 \exp(-B/E)

MOSFET gate-oxide breakdown, Flash programming, and ZnO memristor filament formation all sit in this regime.

Poole-Frenkel emission: trap-assisted hopping transport. In HfO₂ memristors, oxygen vacancies open these channels. Conduction crosses between two regimes: low-V PF, high-V FN.

SIDRA: memristor LRS (low-R) ≈ continuous filament = ohmic + direct tunneling. HRS (high-R) ≈ ruptured filament = PF + FN. Program voltage (~2 V) forms/breaks the filament; read voltage (~0.1 V) only probes it.

Experiment: Vary the Barrier

Try:

  1. V₀ = 3 eV, d = 1 nm, E = 1 eV. Note T. Exponential decay inside the barrier.
  2. Drop d to 0.5 nm. T rises a million-fold.
  3. Raise d to 2 nm. T essentially zero.
  4. Bring E near V₀ (e.g. V₀ = 2, E = 1.9). Tunneling gets easier.
  5. Set E > V₀: classical over-the-top, T ≈ 1.

Quiz

1/5How does tunneling probability depend on barrier thickness?

Lab Task

Use SiO₂ gate oxide: V0−E=3.1V_0 - E = 3.1 eV.

(a) Compute κ. (m=9.11×10−31m = 9.11 \times 10^{-31} kg, ℏ=1.05×10−34\hbar = 1.05 \times 10^{-34} J·s, 1 eV = 1.6×10−191.6 \times 10^{-19} J.) (b) d=1.5d = 1.5 nm → TT? (c) d=1.0d = 1.0 nm → TT? Ratio?

Answers

(a) κ≈9.0×109\kappa \approx 9.0 \times 10^{9} m⁻¹.

(b) 2κd=272\kappa d = 27. T≈e−27≈1.9×10−12T \approx e^{-27} \approx 1.9 \times 10^{-12}.

(c) 2κd=182\kappa d = 18. T≈e−18≈1.5×10−8T \approx e^{-18} \approx 1.5 \times 10^{-8}. Ratio: ~10⁴ — a 0.5 nm difference multiplies current by 10,000×.

Cheat Sheet

  • Tunneling: wave-probability of crossing an insulator.
  • T≈e−2κdT \approx e^{-2\kappa d} — exponential in thickness.
  • κ=2m(V0−E)/ℏ\kappa = \sqrt{2m(V_0-E)}/\hbar — taller barrier, larger κ.
  • HfO₂ high-k: ε_r ≈ 25 → thicker film at same C → 10310^3-10410^4× less leakage.
  • SIDRA memristor: LRS ≈ continuous filament; HRS ≈ broken (PF + FN).
  • Program vs read: ~2 V programs (FN), ~0.1 V reads (ohmic/PF).

Vision: Engineered Tunneling

Tunneling isn’t only a leakage problem — it’s used on purpose:

  • Resonant Tunneling Diode (RTD): two-barrier quantum well; negative differential resistance; high-f oscillator.
  • Tunnel FET (TFET): band-to-band tunneling; sub-60 mV/dec subthreshold beneath the MOSFET physical floor.
  • Quantum-well lasers: tunneling injection; today’s fiber lasers.
  • Josephson junction: superconductor-insulator-superconductor tunneling; the basis of quantum qubits.
  • STT-MRAM / MTJ: magnetic tunnel junction resistance — an alternative to SIDRA’s memristor.
  • Flash write: deliberate FN tunneling to pump electrons into a floating gate (today’s NAND).
  • Scanning Tunneling Microscope (STM): single-atom imaging + manipulation; the measurement tool for tomorrow’s atomic memristor.
  • Tunneling ADC: ultra-low-power analog-to-digital converter for 4 K cryogenic AI interfaces.
  • Proton tunneling: in enzyme catalysis — the quantum component of biological compute.

Biggest lever for post-Y10 SIDRA: an RTD-based selector + memristor — replace OTS with RTD. Sharper NDR threshold, sub-1 ns switching, 10⁵× leakage ratio. Crossbar sneak-path is solved completely. 2028–2030 horizon.

Further Reading