🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.4 · 9 min read

UNAM 4-Layer BEOL (Y1)

SIDRA's heart at the UNAM workshop — HfO₂ memristor production.

Prerequisites

What you'll learn here

  • Map the UNAM workshop's 4-layer BEOL flow
  • Identify the HfO₂ ALD reactor and its workflow
  • Sequence DUV lithography + ICP-RIE etch + CMP + PVD Cu stages
  • State time, equipment, personnel needs per stage
  • Identify investment for UNAM capacity growth

Hook: UNAM = SIDRA's Silicon Lab

UNAM (National Nanotechnology Research Center, Bilkent): Türkiye’s main nanotechnology center. The physical home of the SIDRA workshop.

Task: add HfO₂ memristor BEOL to bare-CMOS wafers from TSMC.

3 weeks, 4 main layers (HfO₂ + M3 + M4 + pad). This chapter goes deep.

Intuition: 4 Layers + 3 Weeks 

Week 5 (wafer arrives from TSMC):
    Day 1: Intake test + clean.
    Day 2-3: HfO₂ ALD (active memristor).
    
Week 6:
    Day 4-5: DUV lithography (memristor pattern).
    Day 6: ICP-RIE etch (remove unwanted HfO₂).
    Day 7: CMP planarization.
    
Week 7:
    Day 8-9: M3 PVD Cu + litho + etch.
    Day 10-11: M4 PVD Cu + litho + etch.
    Day 12: Pad opening + final testing.

After 3 weeks, a complete SIDRA Y1 wafer.

Formalism: Per-Stage Detail

L1 · Başlangıç

HfO₂ ALD (Atomic Layer Deposition):

ALD reactor:

  • Precursor: Tetrakis(dimethylamino)hafnium (TDMAHf) + H₂O.
  • Temperature: 300°C.
  • Cycle: 1 Å/cycle.
  • 5 nm HfO₂ = 50 cycles × 5 s = 4 min active + 2-hour setup.

Uniformity: ±1% across the wafer. Critical for yield.

Y1 UNAM: 2 ALD reactors in parallel. Daily 2 wafers.

DUV lithography (193 nm):

Stepper (1 reticule at a time):

  • Resist coat: 100 nm.
  • Expose: 193 nm UV.
  • Develop: NaOH solution.
  • Hard bake.

Time: 1 hour/wafer (resist + expose + develop).

Stepper at Y1: used ASML 193 nm ~$5M.

ICP-RIE etch:

Plasma etch of HfO₂ with BCl₃ + Ar:

  • Etch rate: 30 nm/min.
  • Selectivity (photoresist): S ~30.
  • 5 nm HfO₂: 10 s (+ pattern transfer).

Result: patterned HfO₂ layer (memristor-shaped).

CMP (Chemical Mechanical Planarization):

Wafer planarization:

  • Slurry: silica + H₂O₂.
  • Pad: polyurethane.
  • Pressure + rotation 2 min.

Mandatory after every metal layer (for a flat surface for the next).

L2 · Tam

M3 PVD Cu + lithography:

M3 = bit-line metal (crossbar columns):

  • PVD sputter Cu: 50 nm.
  • Thin TaN barrier.
  • Resist + DUV stepper.
  • Etch.
  • CMP.

Each metal layer ~1 day.

M4 PVD Cu:

M4 = word-line (rows). Same as M3, perpendicular direction.

M3 and M4 intersections at the HfO₂ cell = crossbar.

Pad opening:

Final step: pad openings to the outside world.

  • Al pad (bond-wire compatible) or Cu.
  • Passivation (SiN protection).
  • Pad opening.

Wafer output:

Per wafer = 38 dies × SIDRA Y1. Active memristor layer + 3 metals + pad. TSMC substrate + UNAM BEOL complete.

Equipment cost:

EquipmentY1 UNAMY10 mini-fab
ALD reactor2 × $500K8 × $500K
DUV stepper1 × $5M (used)2 × $15M (new)
ICP-RIE1 × $300K4 × $500K
CMP1 × $200K4 × $400K
PVD sputter1 × $400K4 × $600K
Test + metrology1 × $500K2 × $2M
Total equipment~$7M~$50M
L3 · Derin

Personnel:

RoleY1 UNAMY10 mini-fab
Process engineer520
Equipment engineer315
Technician540
Test210
Management210
Total1795

UNAM university environment → PhD students also contribute (education + production).

Yield control:

After each layer:

  • Optical inspection (OTP): particles, defects.
  • Electrical test (4-probe): conductance.
  • Error → layer reprocess (rework).

Typical rework rate: 10% (first-pass 90% success).

Chemical safety:

BCl₃ (toxic gas) → special scrubber. NaOH (caustic) → PPE. Cu slurry → wastewater management.

UNAM infrastructure (Bilkent) provides these. ~$500K extra.

Maintenance schedule:

  • Daily: cleanup, calibration.
  • Weekly: precursor change.
  • Monthly: vacuum pump.
  • Yearly: major maintenance (chamber replace).

Typical equipment downtime ~5%. Doesn’t disturb 250 wafers/year capacity.

Y10 mini-fab scale-up:

4× ALD, 2× stepper, 4× others → 10× capacity. 2500 wafers/year.

Cost: 50Mequipment+50M equipment + 20M building. Opex $10M/year (100 personnel).

ROI: 1M chips/year × 150=150 = 150M/year revenue. 5-year payback.

UNAM’s role:

  • Y1: full workshop at Bilkent.
  • Y3: UNAM 2× capacity.
  • Y10: mini-fab in Ankara (TÜBİTAK/ASELSAN partnership).
  • Y100: full fab (industrial zone).

UNAM stays as research + pilot. Production shifts to mini-fab.

Experiment: One UNAM Week

Week 5 (5 new wafers from TSMC):

Monday:

  • Morning: intake inspection (5 wafers).
  • Afternoon: ALD reactor #1 setup.

Tuesday:

  • ALD reactor #1: wafers 1+2 HfO₂ deposition (4 hours each).
  • Afternoon: ALD reactor #2 setup, wafers 3+4 begin.

Wednesday:

  • ALD wafer 5 (reactor #1).
  • Other 4 wafers resist coat for DUV stepper.

Thursday:

  • DUV stepper: 5 wafers in sequence (1 hour each).

Friday:

  • ICP-RIE etch 5 wafers (10 min each + 20 min chamber prep).
  • CMP queue.
  • Weekend: reactor maintenance.

Output: 5 wafers completed HfO₂ stage. Next 2 weeks M3-M4-pad.

Quick Quiz

1/6UNAM workshop's role?

Lab Exercise

UNAM workshop expansion plan.

Scenario: in 2027, the Y1 100K/year target requires 16× workshop growth.

Strategies:

(a) Expand existing UNAM floor: $5M additional ALD + DUV. 2× capacity.

(b) New UNAM branch in Istanbul: $10M new workshop. 8× UNAM capacity.

(c) Mini-fab in Ankara: $70M. 20× UNAM capacity (already Y10 target).

(d) Hybrid: UNAM 2× + mini-fab 10×. $80M total.

Pick: (d) recommended. UNAM kept for research + pilot; production shifts to mini-fab. Gradual transition.

Cheat Sheet

  • UNAM: Bilkent, SIDRA workshop.
  • BEOL 4 layers: HfO₂ + M3 + M4 + pad.
  • Time: 3 weeks/wafer.
  • Weekly: 5 wafers/UNAM.
  • Annual: 250 wafers = 7K chips.
  • Equipment: ~$7M.
  • Y10 mini-fab target: 20× capacity, $70M.

Vision: From UNAM to a Fab

  • Y1: UNAM workshop.
  • Y3: UNAM + small satellite (Istanbul).
  • Y10: Ankara mini-fab.
  • Y100: Full fab in an industrial zone.
  • Y1000: Multi-fab Türkiye network.

Further Reading