🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.8 · 9 min read

Fab Line Simulation

Module 7's closing dive — the annual production-planning game.

Prerequisites

7.7 — Packaging — FC-BGA

What you'll learn here

Tie Module 7's 7 chapters into a single annual production plan
Explain WIP (Work In Progress) and schedule management
Run bottleneck analysis and capacity optimization
State cost-time trade-offs
Prepare for Module 8 (context)

Hook: Module 7's Whole Line

Module 7 covered 7 chapters: cleanroom → wafer journey → TSMC → UNAM → mini-fab → test → packaging. This chapter folds them all into one annual production plan.

Scenario: SIDRA’s 2027 production planning.

Intuition: 100K-Chip Annual Production

Year start: target 100K chips.
↓ Supplier orders (TSMC, materials).
↓ Workshop + mini-fab capacity reserved.
↓ Monthly 8K chip flow.
↓ Year-end: 100K chips shipped.

All of Module 7 combined.

Formalism: Annual Plan

L1 · Başlangıç

Supply chain:

Item	Supplier	Annual amount
TSMC wafers	TSMC Taiwan	4000 wafers
HfO₂ precursor	Sigma-Aldrich	200 L
Cu sputter target	Materion	50 kg
Photoresist	DOW	100 L
Slurry (CMP)	Cabot	500 L
BGA balls	Heraeus	200K packages worth

Supplier schedule: orders 3-6 months ahead.

Production flow (monthly):

TSMC order: 350 wafers (12-month delivery).
UNAM 350 wafers/month = 80 wafers/week.
Test + dicing: 350 × 0.95 = 333 wafers.
Packaging: 333 × 28 dies × 0.95 = 8855 packages.
System test: 8855 × 0.95 = 8412 chips/month.
Annual: 8412 × 12 = 100K chips.

WIP (Work In Progress):

12-week cycle → at any time 12-weeks × 80 wafers/week = ~1000 wafers in-progress (different stages).

L2 · Tam

Bottleneck analysis:

Stage	Capacity	Utilization
TSMC	350 wafers/month (order)	100% (target)
UNAM ALD	100 wafers/month (2 reactors)	350% → bottleneck
UNAM DUV	200 wafers/month (1 stepper)	175% → bottleneck
Test ATE	1000 wafers/month	35%
Packaging	500 packages/day	60%

UNAM ALD + DUV → bottleneck. Investment needed:

2 extra ALD reactors: $1M.
1 extra DUV stepper: $5M.
Total $6M solves the bottleneck.

Cost/chip:

TSMC wafer: $1000/wafer / 28 =$ 36.
UNAM BEOL: $20.
Test: $10.
Packaging: $50.
Logistics: $5.
Fixed (personnel, building): $100K/month / 8K chips =$ 12.
Margin: $50.
Customer price: $183.

100K chips × $183 = **$ 18.3M/year revenue**. Healthy revenue for a UNAM workshop.

Schedule:

Jan 2027: TSMC order #1 (for February production).
Feb: TSMC production starts.
Mar: TSMC wafer #1 delivered. UNAM BEOL starts.
Apr: UNAM completes. Test.
May: Taiwan packaging.
Jun: Türkiye system test. First 8K chips ship.
...
Dec: 100K chips total shipped.

Continuous pipeline. December must plan January.

L3 · Derin

Risk management:

Risk	Probability	Impact	Mitigation
TSMC capacity shortage	20%	All production stops	Samsung backup
UNAM equipment fail	10%	1-month slowdown	Spare parts inventory
Taiwan logistics	5%	2-week delay	Stock buffer
Yield drop	15%	Output drops	Process improvement
No market demand	10%	Inventory build-up	Flexible production

Total risk: estimated 5-10% production loss/year.

Capacity growth plan:

Year 1 (2027): 100K chips. UNAM capacity limit. Year 2 (2028): 200K chips. UNAM 2× growth. Year 3 (2029): 500K chips. Mini-fab pilot. Year 4 (2030): 1M chips. Mini-fab serial (Y10 generation). Year 5 (2031): 5M chips. Y10 mature.

Personnel needs:

2027: 17 (UNAM).
2028: 30.
2029: 60 (mini-fab transition).
2030: 95 (mini-fab full).
2031: 120.

Turkish engineering university grads → employment.

Y10+ strategic vision:

Post-2030 Y10 mini-fab → 1M chips/year. SIDRA becomes the backbone of Türkiye’s semiconductor ecosystem.

Y100 (2035) full fab → 10M chips/year. Global market entry.

Module 7 → 8 bridge:

Module 8 (Context and Future) explores the geopolitical, ethical, and visionary dimensions of this production infrastructure. Semiconductors aren’t just technical; political, economic, social context.

Experiment: 2027 Monthly Plan

January 2027:

Supplier orders.
Personnel training.

February-May:

Pilot pipeline runs. First 5K chips.

June-December:

Full production. 8-10K monthly.

Total 2027: 100K chips ✓.

Revenue: $18.3M. **Net profit (post-opex):**$ 5M. Investment payback: UNAM $5M /$ 5M = 1 year.

Conclusion: Y1 production economically sound. Y10 mini-fab transition justified.

Module 7 Closing Quiz

1/6Module 7's main message?

Integrated Lab: 2030 Y10 Production Scenario

You’re SIDRA Y10 mini-fab manager. Plan 2030.

Target: 1M chips/year.

Plan:

(a) Suppliers: TSMC 14 nm wafers 36K wafers/year × $5K =$ 180M procurement. (b) Mini-fab capacity: 100 wafers/day = 25K wafers/year. Capacity short (36K vs 25K). UNAM extra 11K? Or shrink Y10 die. (c) Test, packaging domestic (BİLGEM partner). (d) Personnel: 95 (chapter 7.5). (e) Revenue: 1M × $500 =$ 500M. Profit: $500M −$ 200M (procurement + opex) = $300M/year. Excellent.

Conclusion: Y10 has $300M/year profit potential. Foundation of Türkiye’s semiconductor industry.

Module 7 Cheat Sheet

8 chapters in summary:

7.1 Cleanroom + ISO classes.
7.2 3-month wafer journey.
7.3 TSMC MPW.
7.4 UNAM BEOL.
7.5 METU CMP mini-fab.
7.6 Test + characterization.
7.7 FC-BGA packaging.
7.8 Fab line sim (this).

Module 7 message: SIDRA Y1 hybrid (TSMC + UNAM + Taiwan). Y10 domestic mini-fab. Y100 full fab. Türkiye’s semiconductor sovereignty path.

Vision: From Production to Context

Module 7 is production. Module 8 (Context): why, for whom, where to?

Geopolitics (US-China semiconductor war).
Türkiye strategic position.
Ethics (responsible acceleration).
Y100 photonic vision.
Your place.

5 chapters later, the SIDRA Atölye education platform completes.

Prerequisites

What you'll learn here

🪝 Hook: Module 7's Whole Line

🧭 Intuition: 100K-Chip Annual Production

📐 Formalism: Annual Plan

🧪 Experiment: 2027 Monthly Plan

📝 Module 7 Closing Quiz

🛠️ Integrated Lab: 2030 Y10 Production Scenario

🗂️ Module 7 Cheat Sheet

🔮 Vision: From Production to Context

📚 Further Reading