Digital Twin / Simulator

Fast simulator:

class FastSimulator:
    def __init__(self, compiled_model):
        self.weights = compiled_model.weights  # INT8
        self.layers = compiled_model.layers
    
    def infer(self, x):
        for layer in self.layers:
            if layer.type == "MVM":
                w = self.weights[layer.idx]
                x = np.dot(w, x)  # plain numpy MVM
            elif layer.type == "ReLU":
                x = np.maximum(0, x)
            # ...
        return x

Fast prototyping. No noise, no IR drop. But functional correctness is guaranteed.

Accurate simulator:

class AccurateSimulator(FastSimulator):
    def infer(self, x):
        for layer in self.layers:
            if layer.type == "MVM":
                w = self.weights[layer.idx]
                # Add noise
                noise = np.random.normal(0, 0.05 * w.std(), w.shape)
                # IR drop simulation
                ir_drop = self.estimate_ir_drop(layer)
                x = np.dot(w + noise + ir_drop, x)
                # Quantization error
                x = self.quantize(x, bits=8)
            # ...

Realistic accuracy. For model validation. Run hundreds of times (Monte Carlo).

Cycle-accurate simulator:

RTL (Register Transfer Level) Verilog/SystemC. Simulates each clock cycle:

always @(posedge clk) begin
    if (mvm_start) begin
        // All crossbar cells in parallel
        for (int c = 0; c < 256; c++)
            current[c] = sum(weights[row][c] * voltage[row]);
        // ...
    end
end

Very slow (1 s of simulation = 10 µs real time) but 100% hardware verification.

Verilator is the open-source alternative (commercial: Synopsys VCS, Cadence Xcelium).

Monte Carlo analysis:

Noise is random → run 100 inferences, observe the accuracy distribution:

accuracies = []
for _ in range(100):
    sim = AccurateSimulator(model, seed=random())
    acc = sim.benchmark(test_data)
    accuracies.append(acc)

print(f"Mean: {mean(accuracies):.2%}, Std: {std(accuracies):.2%}")
# Output: Mean: 97.5%, Std: 0.3%

Worst-case analysis:

Simulate scenarios where the model is sensitive (high temperature, max IR drop, aged device). SIDRA gating criterion: worst-case 95% accuracy.

FPGA prototyping:

If the cycle-accurate sim is too slow, use FPGA. The SIDRA RTL is loaded onto Xilinx/Intel FPGA — it’s 10× slower than real-time but behavioral.

The SIDRA Y1 FPGA prototype was completed in 2025. The software stack was tested on top.

Digital twin ecosystem:

PyTorch Model
    ↓
Compiler (6.7)
    ↓ compile
Compiled Binary
    ↓ deploy
[Fast Simulator]  OR  [Accurate Simulator]  OR  [FPGA]  OR  [Real Y1]

A developer uses the same binary across targets. As fidelity grows:

• Fast: prototype.
• Accurate: pre-release.
• FPGA: production validation.
• Real Y1: deployment.

QAT + simulator loop:

while not acceptable:
    model = train(model)
    model = quantize(model, method="qat")
    compiled = compile(model)
    acc = accurate_simulator.benchmark(compiled)
    if acc < target:
        # Noise injection training
        train_with_noise(model, noise_std=0.05)

Multi-Y1 simulation:

For multi-chip models, the simulator handles independent chips + models PCIe delay.

Performance model:

Simulator also estimates performance:

sim.estimate_latency(model)  # "5 ms / inference"
sim.estimate_energy(model)   # "20 mJ / inference"
sim.estimate_throughput()    # "3000 inferences / second"

Pre-sale spec for customers.

Open source:

SIDRA fast simulator is MIT-licensed — shared with everyone. Researchers can develop without SIDRA hardware.

GitHub: sidra/sidra-sim. PyPI: pip install sidra-sim.

Turkish academic use:

With the simulator open, Turkish students can write SIDRA theses and publish papers without hardware access. A catalyst for the Turkish academic ecosystem.