🧪 Module 2 · Chemistry and Materials Science · Chapter 2.8 · 12 min read

Metallization — Tungsten vs Copper

The electron's journey — which metal goes where, and why?

Prerequisites

What you'll learn here

  • Compare electrical and thermal properties of Cu, W, and Al
  • Explain why each BEOL layer uses the metal it does
  • Use Black's equation to estimate electromigration lifetime
  • Describe the TaN/Ta barrier system and the Cu damascene flow
  • Plan metal choices for SIDRA's 20-layer BEOL stack

Hook: The Electron's Telegraph Wires

A transistor is 10 nm across; a SIDRA chiplet diagonal is 28 mm. For a bit to travel from one corner to the other, that’s 2.8 million transistor widths. If you don’t choose the right wire:

  • High resistance → voltage drops, signal distorts, slows down.
  • High capacitance → RC delay reduces clock rate.
  • High current density → the metal “flows like sand” (electromigration) and eventually breaks.

Each BEOL layer has a different need. Lower layers want small, dense, high-T tolerant metal (tungsten). Mid-upper layers demand speed and efficiency (copper dominates). The top pad sometimes goes back to aluminium.

This chapter answers “why not one metal everywhere?” — and explains the design of SIDRA’s 20-layer Cu stack.

Intuition: Three Metals, Three Roles

MetalResistivity (μΩ·cm, bulk)Thermal tolerancePrimary role
Al (aluminium)2.65< 350°C annealOlder chips, today mostly pad metal + fuses
Cu (copper)1.68 (lowest practical)< 400°C (diffusion risk)Main BEOL interconnect, mid-upper metal layers
W (tungsten)5.3Up to 700°CContact plug (transistor → metal-1), lowest vias

Intuitions:

  • Copper is the best conductor, but it diffuses into silicon (slips into the crystal lattice) → kills the transistor. So every Cu layer is clad with a TaN barrier.
  • Tungsten is refractory (MP 3422°C), doesn’t diffuse, and stays well-behaved in small vias. Its resistivity is 3× higher — bad for long wires, ideal for short vertical contacts.
  • Aluminium is “vintage” today — mostly for pad metal and ESD protection. Electromigration lifetime is 10³-10⁴× worse than Cu at the same temperature.

In SIDRA:

  • V1 contact → M1 → V2: W contact + TaN/Cu (transition layer).
  • M2-M18: TaN/Cu (damascene).
  • M19-M20: wider pitch, Cu or Al. SIDRA picks Cu.
  • Pad: Al (bond-wire compatible) or NiAu.

Formalism: Resistance, RC, Electromigration

L1 · Başlangıç

A metal line:

R=ρ⋅LAR = \rho \cdot \frac{L}{A}
  • ρ\rho — resistivity (μΩ·cm)
  • LL — length
  • AA — cross-section

Cu 40 nm × 40 nm × 1 mm: R=1.68×10−8 Ω⋅m×10−3 m/(40×40×10−18 m2)=10.5 ΩR = 1.68 \times 10^{-8}\ \Omega\cdot\text{m} \times 10^{-3}\ \text{m} / (40 \times 40 \times 10^{-18}\ \text{m}^2) = 10.5\ \Omega

Same line in W: R=33R = 33 Ω. 3× slower.

L2 · Tam

RC delay:

τ=R⋅C\tau = R \cdot C

A metal line carries both resistance R and parallel capacitance C (to neighbors + ground). τ is the line’s charge/discharge time; it caps the signal rate.

SIDRA M2 (narrow lower-mid line, 30 nm width, 30 nm thickness, 1 mm length — size effect gives ρ_eff ≈ 3.5 μΩ·cm):

  • A=30×30=900 nm2=9×10−12 cm2A = 30 \times 30 = 900\ \text{nm}^2 = 9 \times 10^{-12}\ \text{cm}^2
  • R=ρL/A=3.5×10−6×0.1/9×10−12≈39 kΩ/mmR = \rho L / A = 3.5 \times 10^{-6} \times 0.1 / 9 \times 10^{-12} \approx \mathbf{39\ k\Omega/mm}
  • C ≈ 0.15 pF/mm (low-k dielectric, tight pitch)
  • τ=RC≈39×103×0.15×10−12≈5.8 ns/mm\tau = RC \approx 39 \times 10^3 \times 0.15 \times 10^{-12} \approx \mathbf{5.8\ ns/mm}

For a 5 GHz clock (200 ps budget) this line can only span ~34 µm. Beyond that, insert a repeater (inverter buffer) or route up to a wider upper metal like M10, where R drops to 1-2 kΩ/mm.

Electromigration (EM):

At high current density, electrons transfer momentum to metal atoms; atoms drift (“electron wind”). Over time, voids accumulate → the line breaks.

Black’s equation (mid-current lifetime):

MTTF=AJnexp⁡(EakT)\mathrm{MTTF} = \frac{A}{J^n} \exp\left(\frac{E_a}{k T}\right)
  • MTTF\mathrm{MTTF} — mean time to failure (s)
  • JJ — current density (A/cm²)
  • nn — typically 2 (bulk EM)
  • EaE_a — activation energy; Cu ~0.9 eV, Al ~0.5 eV
  • AA — material constant

The EaE_a difference is exponential → Cu lives 10³-10⁴× longer than Al at the same T. That’s why Cu became standard (1997+).

SIDRA current-density limits: Cu at M1-M2 carries ~1 MA/cm²; upper layers ~0.5 MA/cm². The cap comes from the Blech length (short wires can’t develop EM) plus thermal margin.

L3 · Derin

Barrier engineering:

Cu diffuses into silicon → kills the MOS gate oxide. Solution: TaN/Ta bilayer.

  • TaN (5 nm): amorphous, dense, impermeable to Cu (diffusion < 0.1 nm/year at 400°C).
  • Ta (3 nm): good Cu adhesion, nucleation seed.

Alternative: Ru (ruthenium) — barrier + seed combined, < 3 nm. In production since Intel 4/3 nm.

Size effect: as Cu line width drops below 40 nm, resistivity rises (not functionally — physically). Surface scattering and grain-boundary scattering dominate. At 20 nm width, effective ρ ≈ 3 μΩ·cm (1.8× bulk). So thinner isn’t always faster.

Damascene variants:

  • Single damascene: trench only. Mid-upper Cu layers.
  • Dual damascene: trench + via in one litho step. Cheaper, but the fill is harder.
  • Sub-damascene: 5 nm and below — very fine lines, topology constraints.

Barrierless Ru via: Ru doesn’t diffuse into SiO₂ (low diffusion coefficient). No TaN needed → via resistance drops ~30%. Candidate for post-Y10 SIDRA.

Al holdovers: SIDRA Y10 uses Al at the pad layer — bond-wire compatibility and corrosion resistance. Al is 1-2 µm thick here, so ρ stays bulk-limited.

Experiment: Compute M10 Line Delay

A SIDRA M10 line: width 100 nm, thickness 100 nm, length 500 µm.

Cu: ρ = 1.68 μΩ·cm (bulk), with size effect effective ρ = 2.2 μΩ·cm.

Cross-section: A=100×100=10 000 nm2=10−10 cm2A = 100 \times 100 = 10\,000\ \text{nm}^2 = 10^{-10}\ \text{cm}^2.

Resistance: R=ρ⋅L/A=2.2×10−6 Ω⋅cm×500×10−4 cm/10−10 cm2=1100 ΩR = \rho \cdot L / A = 2.2 \times 10^{-6}\ \Omega\cdot\text{cm} \times 500 \times 10^{-4}\ \text{cm} / 10^{-10}\ \text{cm}^2 = 1100\ \Omega.

Capacitance (low-k ε = 2.5, 200 nm pitch): C≈0.1 pFC \approx 0.1\ \text{pF}.

τ=R⋅C=1100×0.1×10−12=110 ps\tau = R \cdot C = 1100 \times 0.1 \times 10^{-12} = 110\ \text{ps}.

5 GHz clock (200 ps period) → this one line eats half the period by itself. Add repeaters or route through a thicker upper layer (lower R).

Same line in Al (ρ = 2.65 → effective ~3.5 μΩ·cm): R ≈ 1750 Ω, τ ≈ 175 ps. 60% slower → can’t run at 5 GHz.

Quick Quiz

1/5Main BEOL interconnect metal in modern CMOS?

Lab Exercise

SIDRA M5 (5th metal): 60 nm × 60 nm × 200 µm Cu line. 5 GHz clock.

ρ_Cu(bulk) = 1.68 μΩ·cm. With size effect, effective ρ = 2.5 μΩ·cm at 60 nm width.

(a) Line resistance? (b) Capacitance 0.2 pF/mm (low-k). Total C? (c) τ = RC? (d) At 5 GHz the clock period is 200 ps. What fraction of the budget does this line eat? (e) Current-density limit 1 MA/cm². Can it carry 10 mA?

Answers

(a) A=60×60=3600 nm2=3.6×10−11 cm2A = 60 \times 60 = 3600\ \text{nm}^2 = 3.6 \times 10^{-11}\ \text{cm}^2. R=ρL/A=2.5×10−6×200×10−4/3.6×10−11=5×10−8/3.6×10−11=1389 ΩR = \rho L / A = 2.5 \times 10^{-6} \times 200 \times 10^{-4} / 3.6 \times 10^{-11} = 5 \times 10^{-8} / 3.6 \times 10^{-11} = \mathbf{1389\ \Omega}.

(b) C=0.2 pF/mm×0.2 mm=0.04 pFC = 0.2\ \text{pF/mm} \times 0.2\ \text{mm} = \mathbf{0.04\ pF}.

(c) τ=RC=1389×0.04×10−12=56 ps\tau = RC = 1389 \times 0.04 \times 10^{-12} = \mathbf{56\ ps}.

(d) 56 / 200 = ~28%. For the critical path this single line is too much — you need repeaters or routing through an upper metal.

(e) 1 MA/cm² × 3.6×10−113.6 \times 10^{-11} cm² = 3.6×10−53.6 \times 10^{-5} A = 36 µA max. 10 mA is vastly above — the wire would fail. You need a wider line or parallel wires (10 mA / 36 µA ≈ 280 parallel lines).

Cheat Sheet

  • Cu: main BEOL interconnect. ρ = 1.68 μΩ·cm, lowest resistance. TaN barrier mandatory.
  • W: contact plug + lowest vias. MP 3422°C, high-T durability. ρ = 5.3 μΩ·cm (3× Cu).
  • Al: pad, ESD, some legacy layers. EM lifetime 10³-10⁴× worse than Cu.
  • Black’s equation: MTTF ∝ A/J^n × exp(E_a/kT). E_a ≈ 0.9 eV for Cu, 0.5 eV for Al.
  • Size effect: below 40 nm, effective ρ rises (surface + grain-boundary scattering).
  • SIDRA: W contact + Cu/TaN mid-upper (M2-M18) + Al/Cu pad. 20 damascene layers.

Vision: Beyond Metal

  • Barrierless Ru via: skip TaN; Ru bonds to SiO₂ directly. Via resistance drops ~30%. Active at Intel 4 nm.
  • Co (cobalt): at sub-7 nm nodes for M1-M2. Avoids Cu size-effect at small widths.
  • CNT interconnect: 1000× higher current density than copper, in theory. Integration still open — alignment, density, consistency.
  • Graphene interconnect: high mobility in 2D; monolayer only so far; still research.
  • Superconductors (Nb, YBCO): zero resistance for 4 K cryogenic AI. Off-table for today’s chips, on for quantum-AI hybrids.
  • Optical interconnect: photonic waveguides skip RC entirely. SIDRA Y100 targets this.
  • Wireless on-chip: mm-wave antennas for chiplet-to-chiplet packaging. Experimental.
  • 3D chiplet TSVs: through-silicon vias filled with Cu; critical for HBM-M.

Biggest lever for post-Y10 SIDRA: barrierless Ru for M2-M5 + photonic M-top. Via resistance drops 30%, upper 3 layers move to silicon photonics → RC delay down 10×, bandwidth up 100×. 2028–2031 horizon.

Further Reading

  • Next chapter: 2.9 — Contamination and the Doom of a Single Speck
  • Previous: 2.7 — CMP and the SOG Alternative
  • Classic: Rosenberg, Edelstein, Hu, Rodbell, Copper metallization for high performance silicon technology, Annu. Rev. Mater. Sci. 2000.
  • Black’s original: J. R. Black, Electromigration — A brief survey and some recent results, IEEE TED 1969.
  • Size effect: Steinhögl et al., Size-dependent resistivity of metallic wires, Phys. Rev. B 2002.
  • Ru via: Zhang et al., Ruthenium interconnects, IEEE IITC 2020.