🧪 Module 2 · Chemistry and Materials Science · Chapter 2.10 · 11 min read

Chemistry Module Review

From the periodic table to the SIDRA workshop door — a map of nine chapters.

Prerequisites

2.9 — Contamination and the Doom of a Single Speck

What you'll learn here

Collapse Module 2's nine chapters onto a single SIDRA-manufacturing-line map
Match each chemistry concept to a real SIDRA process step
Run an end-to-end lab decision exercise to build a HfO₂ memristor layer
Prepare for Module 3 (Biology and Algorithm)

Hook: Nine Chapters → One Production Line

Across Module 2 we covered nine fronts: the chip side of the periodic table, HfO₂, NbOx, ALD/PVD/CVD, lithography chemistry, plasma etching, CMP, metallization, and contamination. They look like separate topics. They are actually the journey of a single wafer through the workshop.

A silicon wafer enters the workshop; HfO₂ is grown atom-by-atom on top; resist is spun, exposed, masked; unwanted regions are stripped by plasma; the surface is flattened by CMP; copper and tungsten run the wires; every step is shielded from a single dust grain or a single ion — and at the end, a SIDRA Y1 die with 419 million cells exists.

This chapter draws that map, condenses it to a one-page cheat sheet, and closes the module with an end-to-end lab decision exercise.

Intuition: One Wafer's Trip Through the SIDRA Workshop

Each chapter maps onto a step in the SIDRA flow:

Chapter	Concept	SIDRA workshop step
2.1	Periodic table, element selection	Why we picked Si substrate, Hf, Nb, Cu, W, Ta, O
2.2	HfO₂ — high-k + memristor double role	Active layer of the 419M cells in Y1 (gate oxide comes from the 28 nm fab)
2.3	NbOx OTS selector	Selector blocking sneak-path in the 1S1R cell
2.4	ALD / PVD / CVD thin films	We grow HfO₂ with ALD, Cu seed with PVD
2.5	Lithography chemistry (resist)	Patterning 100-200 nm features with DUV (193 nm)
2.6	Plasma etching (ICP-RIE)	Removing HfO₂ and metal lines, sub-100 nm precision
2.7	CMP / SOG planarization	Re-flattening the wafer after every metal layer
2.8	Metallization (W, Cu, Al)	W contact + Cu BEOL (M2-M18) + Al pad
2.9	Contamination and yield	Cleanroom discipline that closes those steps at 70% yield

One-sentence summary: Module 1 gave us the physics; Module 2 gave us the means to write that physics onto a wafer. Pick atoms, stack atoms, pattern, etch, flatten, wire, protect. Nine chapters = nine verbs.

Formalism: One-Page Chemistry-Manufacturing Card

L1 · Başlangıç

Nine core relationships, all in one place:

Topic	Key formula / rule
HfO₂ dielectric gain	$C_{ox} = \varepsilon_0 \varepsilon_r / t_{ox}$ , $\varepsilon_r \approx 25$ → 6× thicker film
EOT (equivalent SiO₂ thickness)	$\text{EOT} = t_{\text{real}} \cdot \varepsilon_{SiO_2} / \varepsilon_r$
OTS current threshold	$V > V_{th}$ → current jumps 4-6 decades (NbOx)
ALD growth rate	~1 Å / cycle, self-limiting
Resist resolution	$\text{CD} = k_1 \lambda / \mathrm{NA}$ (Rayleigh)
Etch selectivity	$S = \text{rate(film)} / \text{rate(mask)}$
CMP removal rate	Preston: $R = K_p \cdot p \cdot v$
Metal resistance (Ohm)	$R = \rho L / A$ , Cu: 1.68 µΩ·cm
Black EM lifetime	$\mathrm{MTTF} = A/J^n \exp(E_a/kT)$
Poisson yield	$Y = e^{-A_c D_0}$

L2 · Tam

Chemistry categories in SIDRA context:

Category	SIDRA example	Why we picked it
High-k dielectric	HfO₂ (ε_r ≈ 25)	Gate tunneling drops 10³-10⁴×
Phase-change	NbOx (Mott transition)	OTS selector, 1S1R sneak-path
Self-limiting deposition	ALD (HfO₂, TaN)	Atom-by-atom control, conformal
High-throughput deposition	PVD (Cu seed, Al pad)	Fast, thick films
Structural semiconductor	Si (substrate)	60+ years of infrastructure, perfect lattice
Barrier	TaN/Ta	Stops Cu diffusion
Refractory metal	W (contact)	MP 3422°C, stable in small vias
Low-resistance metal	Cu (BEOL)	1.68 µΩ·cm, best practical conductor
Corrosion-resistant pad	Al (pad)	Bond-wire compatible

Three big control variables:

Temperature — ALD 200-400°C, anneal 600-1000°C, etch near room T. Each step has a thermal budget (so it doesn’t damage the previous layers).
Pressure — vacuum (10⁻⁶ Torr) for PVD/CVD; atmospheric for litho/CMP.
Plasma chemistry — CF₄, Cl₂, O₂ — the choice fixes etch selectivity and sidewall profile.

Module 2’s single connecting line: start from atoms (2.1) → stack atoms (2.4) → pattern what you stacked (2.5) → etch what you want gone (2.6) → flatten what’s left (2.7) → wire it (2.8) → protect it from dirt (2.9). HfO₂ (2.2) and NbOx (2.3) are the special-material lessons along that line.

Experiment: Wafer Journey Concept Map

Take an A4 sheet and draw the flow below. Write one sentence on every arrow:

[Si Substrate (from FEOL fab)]
       │
       ↓  (final CMP planarization)
[Workshop intake test]
       │
       ↓  (Ch. 2.4: ALD HfO₂ ~5 nm)
[HfO₂ active layer]
       │
       ↓  (Ch. 2.5: DUV resist + mask)
[Patterned resist]
       │
       ↓  (Ch. 2.6: ICP-RIE plasma etch)
[Patterned HfO₂]
       │
       ↓  (Ch. 2.4: PVD Cu seed)
[Cu seed layer]
       │
       ↓  (Ch. 2.8: Cu damascene + TaN barrier)
[1T1R cells wired]
       │
       ↓  (Ch. 2.7: CMP planarization)
[Flat surface]
       │
       ↓  (× 17 layer repeat)
[20-layer BEOL stack]
       │
       ↓  (Ch. 2.5: pad mask)
[Al pad opened]
       │
       ↓  (Ch. 2.9: e-test, yield measurement)
[Tested wafer]
       │
       ↓  (Dicing → 38 dies)
[SIDRA Y1 dies — 27 good]

Each arrow corresponds to its own sub-equipment: ALD reactor, DUV stepper, RIE chamber, CMP polisher, electroplating tank, SEM, e-test prober. This map is foundational for Module 7 (Manufacturing & Ecosystem).

Comprehensive Quiz

In Module 2, each question tests 2-3 chapters. 8 questions — pass with more than half.

1/8We grow HfO₂ with ALD. What is ALD's main advantage?

Integrated Lab: Choose How to Build the HfO₂ Layer

You are SIDRA’s process engineer. For Y1 wafers’ HfO₂ memristor layer, decide the following five questions.

Mission parameters:

Target HfO₂ thickness: 5 nm
Target device: 100 nm × 100 nm 1T1R cell
Wafer size: 200 mm
Workshop class: ISO Class 5
Budget: minimize material + equipment hourly rate
Quality: layer endurance ≥ 10⁶ cycles

Decisions:

(a) Deposition method: ALD, PVD, or CVD? Why?

(b) Temperature: to avoid damaging Y1’s 28 nm CMOS substrate transistors, BEOL thermal budget caps at 400°C. For ALD HfO₂, choose 250°C, 300°C, or 350°C.

(d) Patterning: is DUV (193 nm) enough, or is multi-patterning (LELE) required? CD = k₁·λ/NA, with k₁ = 0.35, NA = 1.35.

(e) Etch chemistry: BCl₃ (high selectivity, slow), or CHF₃ (medium selectivity, fast)?

Solutions

(a) ALD. Self-limiting → exact 5 nm; conformal (matters for downstream topography); film uniformity is far better than PVD for endurance. ALD costs 3-5× more than PVD but at Y1 volume that’s negligible.

(b) 300°C. 250°C guarantees HfO₂ amorphous structure but precursor pyrolysis is incomplete → carbon residue. 350°C lets the film start crystallizing (monoclinic — small grain-boundary leakage). 300°C is the sweet spot.

(c) HfAlO (10% Al). Pure HfO₂ endurance is ~10⁵ (filament over-clusters). HfZrO triggers the ferroelectric phase — we don’t want that (we’re not FeFET). Al-doping spreads the filament population, raising endurance into the 10⁶-10⁷ range.

(d) CD_min = 0.35 × 193 / 1.35 = 50 nm. More than enough for a 100 nm cell — single-patterning DUV does the job. Multi-patterning becomes mandatory at Y10 (28 nm target needs CD 14 nm, even k₁ = 0.25 still leaves 36 nm — LELE required).

(e) BCl₃. For HfO₂ etch, BCl₃ + Ar plasma gives high selectivity (S > 30 over photoresist). CHF₃ is faster but leaves polymer residue on sidewalls → 5% CD shift on a 100 nm cell. We can’t tolerate that at Y1 precision.

Conclusion: ALD @ 300°C with 10% Al-doped HfO₂, DUV single patterning, BCl₃ etch. This recipe hits the Y1 yield budget (HfO₂ layer 85%+).

Module 2 Cheat Sheet

At-a-glance gains:

✅ The chip-friendly corner of the periodic table (Si, Hf, Nb, Cu, W, Ta, O).
✅ HfO₂ — high-k dielectric + memristor active layer double role.
✅ NbOx — Mott transition, OTS selector, 1S1R sneak-path control.
✅ ALD / PVD / CVD — deposition technologies and which layer each grows.
✅ Lithography chemistry — DUV resist, OPC, CD = k₁λ/NA.
✅ Plasma etching — ICP-RIE, selectivity, sidewall profile.
✅ CMP + SOG — planarization after every metal layer.
✅ Metallization — W contact, Cu BEOL (TaN barrier), Al pad, EM lifetime.
✅ Contamination and yield — Poisson model, ISO 14644, Y1 ~70% yield.

Ready for the SIDRA workshop: Module 7 revisits these processes through the workshop-fab economics lens; Module 5 turns the electrical behavior of these materials into circuit design.

Vision: Beyond Chemistry — Preview of Modules 3-9

Module 2 covered the path from atom to wafer. The next modules turn that wafer into a meaningful compute engine — each a possible leap point for post-Y10 SIDRA:

Module 3 (Biology to Algorithm): synapse, STDP, Hebbian. Vision: organic PEDOT:PSS synapse, bio-compatible neuromorphic chip, brain-budget 20 W AI systems.
Module 4 (Math Arsenal): linear algebra, probability, optimization, tensor. Vision: analog-aware optimizer, stochastic-MAC, quantum-classical hybrids.
Module 5 (Chip Hardware): 1T1R, crossbar, ADC, TDC, sense-amp. Vision: 1024×1024 crossbar, 256-level analog, photonic-electronic hybrid MVM.
Module 6 (Software Stack): compiler, mapping, mixed precision. Vision: automatic analog-aware compiler, hardware-software co-design.
Module 7 (Manufacturing & Ecosystem): workshop → mini-fab → fab. Vision: Türkiye 200 mm fab (2030), 300 mm chiplet line (2035).
Module 8 (Context & Future): supply chain, geopolitics, brain-computer. Vision: national semiconductor sovereignty, brain-friendly interface, post-CMOS era.

Module 2’s biggest “lever” for SIDRA? The HfO₂ ALD recipe. This single material + this single process step carries SIDRA Y1’s entire differentiation. Scaling the same recipe onto the 28 nm CMOS substrate for Y10 is an 18-24 month effort. By Y100 we’ll have moved on to HZO ferroelectrics or CNT-reinforced HfO₂ — but when that day comes, the same workshop, the same ALD chamber, the same cleanroom discipline will still be the platform.

Bet on the unexpected future: self-assembling memristors. DNA-directed HfO₂ filament growth — sub-atomic precision, zero lithography. 2030+ horizon, but the SIDRA workshop’s chemistry stack is positioned for it.

Prerequisites

What you'll learn here

🪝 Hook: Nine Chapters → One Production Line

🧭 Intuition: One Wafer's Trip Through the SIDRA Workshop

📐 Formalism: One-Page Chemistry-Manufacturing Card

🧪 Experiment: Wafer Journey Concept Map

📝 Comprehensive Quiz

🛠️ Integrated Lab: Choose How to Build the HfO₂ Layer

🗂️ Module 2 Cheat Sheet

🔮 Vision: Beyond Chemistry — Preview of Modules 3-9

📚 Further Reading