🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.7 · 8 min read

Packaging — FC-BGA

From bare die to customer chip — flip-chip ball-grid array.

Prerequisites

What you'll learn here

  • Sequence FC-BGA packaging steps (bumping, flip, underfill, balling)
  • Identify substrate and heat-spreader roles
  • State equipment and step times
  • Discuss Taiwan outsourcing vs Türkiye in-house packaging
  • Outline the Y10+ heterogeneous packaging (CoWoS) path

Hook: Packaging Makes the Chip Customer-Ready

A die from the wafer: 10 mm × 10 mm of silicon. How does the customer mount that on a PCB? Packaging.

For Y1: FC-BGA (Flip-Chip Ball Grid Array). 30 mm × 30 mm package, ~1500 pins.

This chapter covers the physical packaging flow.

Intuition: Packaging in 4 Steps 

Bare die (from UNAM)
    ↓ 1. Wafer bumping (solder balls on pads)
    ↓ 2. Wafer dicing (individual dies)
Die
    ↓ 3. Flip + bond (onto substrate)
    ↓ 4. Underfill (epoxy)
    ↓ 5. Heat spreader + lid
    ↓ 6. Ball attach (BGA balls underneath)
    ↓ 7. Final test
Packaged chip

In Taiwan, Amkor/ASE do this. Time: 2 weeks.

Formalism: Packaging Steps

L1 · Başlangıç

1. Wafer bumping:

Solder balls placed on the pads:

  • Cu pillar (15 µm).
  • SnAg solder cap (5 µm).
  • Pitch typically 100 µm.

A Y1 die has ~1500 bumps. Bumping per wafer = 30 min.

2. Wafer dicing:

Diamond saw or laser → individual dies. UNAM or Amkor does it.

3. Flip + bond:

Die “face down” → onto the substrate. Solder reflow (240°C) bonds.

4. Underfill:

Fill the gap between die and substrate with epoxy. Thermal-stress relief.

5. Heat spreader:

Cu plate sticks on top → heat spreading.

6. Ball attach:

BGA solder balls on the bottom of the substrate. Soldered to the PCB.

7. Final test:

Package test (chapter 7.6).

L2 · Tam

Packaging materials:

  • Substrate: BT (Bismaleimide-Triazine) or FR4 → multi-layer (4-12).
  • Solder: SnAgCu (lead-free, RoHS).
  • Underfill: epoxy.
  • Heat spreader: Cu, Ni-coated.
  • BGA balls: SAC405 solder.

Y1 package cost:

  • Substrate: $20.
  • Bumping: $5.
  • Assembly: $15.
  • Test: $10.
  • Total: ~$50/package (Taiwan Amkor).

100K packages/year = 5Mpackaging.PlusTu¨rkiyelogistics+customs+transferextra5M packaging. Plus Türkiye logistics + customs + transfer extra 5/package.

Türkiye in-house packaging:

  • BİLGEM has a pilot pkg lab (limited).
  • Investment: $10M single-line FC-BGA setup.
  • Capacity: 100K packages/year sufficient.
  • Cost: $40/package (logistics savings).

Y3+ goal: domestic packaging (BİLGEM partnership).

L3 · Derin

Y10 heterogeneous integration:

Y10 target: SIDRA + HBM3 + I/O die in one package = CoWoS (TSMC patent).

Process:

  1. Interposer wafer (Si, passive routing only).
  2. Multi-die bond on interposer.
  3. Bond to substrate.

More complex + expensive (~$500/package).

Y100 3D stack:

8 SIDRA dies stacked, connected via TSV. Thermal challenge.

Packaging: $1000+/package. Complex supply chain.

Test in packaging:

  • Pre-bumping wafer test.
  • Post-assembly final test (5 min).
  • Burn-in (24 hours @ 85°C, 95% of failures appear in the first hour).

Burn-in catches early failures. SIDRA Y1 mobile/edge typical 4-hour burn-in (short).

Logistics:

Y1 die UNAM → DHL freight → Taiwan Amkor (4 days). Packaged chip Amkor → DHL → Türkiye (4 days). Total packaging cycle: 14 days.

Y3+ domestic packaging: 2-day total.

Pin-count design importance:

Y1: 1500 pins. Y10 target: 3000-5000 pins (HBM extra 1024 pins).

More pins = more package area + cost. Design optimization mandatory.

Experiment: Y1 Package Budget

100 die packaging:

  • Bumping: 100 × 5=5 = 500.
  • Dicing: 100 × 1=1 = 100.
  • Assembly: 100 × 15=15 = 1500.
  • Underfill, lid: 100 × 5=5 = 500.
  • BGA: 100 × 5=5 = 500.
  • Test: 100 × 10=10 = 1000.
  • Total: 4100=4100 = 41/package.

100K packages/year = $4.1M.

Plus Taiwan add-ons (logistics + transfer): 5/package×100K=5/package × 100K = 500K.

Total Taiwan outsourcing: $4.6M/year.

Domestic alternative (BİLGEM): 4M/year(logisticssavings4M/year (logistics savings 600K).

Investment 10M/10M / 600K savings = 17-year payback. Pure economics favors outsourcing. Strategic bonus (domestic capacity) tilts toward in-house from Y3+.

Quick Quiz

1/6What does FC-BGA mean?

Lab Exercise

Y1 package-variant decision.

Customer segments:

  • Mobile (compact, cheap): BGA over plastic QFP. Y1 FC-BGA fits.
  • Datacenter: high pin, cooling. FC-BGA standard.
  • Automotive: AEC-Q100 cert. FC-BGA + extra protection.
  • Space/defense: hermetic seal, radiation-tolerant. Special pkg for Y1.

Decision: FC-BGA suits most. Specific applications get Y3+ package variants.

Cheat Sheet

  • FC-BGA: flip-chip + ball-grid array. Y1 package.
  • Steps: bumping → dicing → flip → underfill → spreader → balling → test.
  • Cost: $50/package (Taiwan).
  • Türkiye in-house: $40 (post-investment).
  • Y10: CoWoS heterogeneous.
  • Y100: 3D stack.

Vision: Domestic Packaging Industry

  • Y1: Taiwan outsourced.
  • Y3: BİLGEM domestic pilot pkg ($10M).
  • Y10: In-house mini-fab packaging + CoWoS outsourcing.
  • Y100: Fully domestic + 3D-stack capacity.
  • Y1000: Wafer-scale (Cerebras-style) → packaging changes entirely.

Further Reading