🏭 Module 7 · Fabrication and Ecosystem · Chapter 7.2 · 9 min read

Three Months of a Wafer

TSMC to UNAM to packaging — the end-to-end production timeline.

Prerequisites

7.1 — Cleanrooms and ISO Classes

What you'll learn here

Walk through a SIDRA Y1 wafer's full production timeline day-by-day
Explain the logistics chain (TSMC-UNAM-Taiwan)
List the wafer-by-wafer process steps
Identify time-critical steps (lithography, CMP, test)
State production-acceleration strategies

Hook: 3 Months from Order to Package

A SIDRA Y1 chip:

Weeks 1-4: TSMC 28 nm CMOS substrate.
Weeks 5-7: UNAM workshop BEOL HfO₂ + memristors.
Weeks 8-9: Wafer test + dicing.
Weeks 10-11: Packaging (Taiwan).
Week 12: Final test + shipment.

Total: 12 weeks = 3 months. Each wafer 38 dies = 27 final chips (after yield).

This chapter details every stage.

Intuition: Multi-Site, Single Flow

TSMC Taiwan: 28 nm CMOS substrate
    ↓ flight (4-week process + 1-week ship)
UNAM Bilkent: BEOL memristor
    ↓ in-house (3 weeks)
ASELSAN test: wafer test
    ↓ flight (1 week)
Amkor Taiwan: packaging
    ↓ flight (2 weeks)
SIDRA test lab: final test + shipment
    ↓ Türkiye + world

Multi-site logistics is complex. Y10+ goal: all-domestic (mini-fab in Türkiye).

Formalism: Wafer Flow

L1 · Başlangıç

Stage 1: TSMC 28 nm CMOS substrate (4 weeks).

Customer (SIDRA): tape-out file (GDS-II) → TSMC → wafer fab.

200 mm wafer, 38-die layout.
28 nm CMOS substrate: transistors, M1-M2 metal.
Multi-Project Wafer (MPW): SIDRA shares wafer with other customers → cheap.

Output: “bare-CMOS” wafer, particle-clean.

Cost: $1000-5000/wafer (MPW shared).

Stage 2: UNAM BEOL (3 weeks).

Wafer arrives at UNAM (air cargo, special crate). At the workshop:

Week 5:

Wafer intake test + clean.
M3 metal layer.
Memristor BEOL: ALD HfO₂ (2 µm active area).

Week 6:

DUV lithography (memristor pattern).
ICP-RIE etch.
CMP planarization.

Week 7:

M4 metal (BL).
M5-M20 upper metal layers.
Pad opening.

Output: full SIDRA Y1 wafer (substrate + BEOL).

L2 · Tam

Stage 3: Wafer test (1 week).

Probe-card test on every die (chapter 6.9):

DC test.
Crossbar reference.
Memory test.

Failed dies marked. Yield: 75% → 28 good dies/wafer.

ASELSAN’s test lab can be used (in Türkiye).

Stage 4: Dicing (2 days).

Wafer cut → individual dies. Diamond saw or laser. UNAM can do it.

Stage 5: Packaging (2 weeks).

Dies sent to Amkor/ASE in Taiwan. FC-BGA (chapter 5.13):

Wafer bumping.
Flip-chip die-to-substrate.
Underfill.
Heat spreader.

Yield: 95% → 26-27 packaged chips/wafer.

Stage 6: Final test (1 week).

Each packaged chip system test:

PCIe enumeration.
Full crossbar test.
Thermal stress.
AI benchmark (MNIST).

Yield: 95% → 25 ship-ready chips/wafer.

Shipment: crate + documentation + certification.

L3 · Derin

Time-critical steps:

Step	Time	Bottleneck
TSMC	4 weeks	Supplier schedule (3-6 months queue)
UNAM ALD	2 hours × 3 layers	Reactor count
Lithography	1 hour × 4 masks	DUV slow, single wafer
Etch	1 hour × 4 layers	RIE chamber
CMP	1 hour × 5 layers	CMP station
Test	30 s × 38 dies = 20 min	Probe card speed
Packaging	2 weeks	Taiwan logistics

Single-wafer total: 3 months. Parallel work-in-progress (WIP) means daily output is 1-2 wafers.

Acceleration:

2× ALD reactors → ALD time halved.
Domestic packaging (mini-fab in Türkiye) → save 2-week logistics.
Domestic TSMC alternative (none today) → 4 weeks → in-house.

Y10 mini-fab cuts the whole cycle to 6 weeks (2× faster).

WIP management:

Workshop runs continuously. Each week 5 wafers in (from TSMC), 5 wafers out (shipping). 12-week look-ahead.

Pipeline: 60 wafers in-progress at any time. Each at a different stage.

Production planning:

class WaferPlanner:
    def schedule(self, target_chips):
        wafers_needed = target_chips / 25  # final yield
        # TSMC order
        order_tsmc(wafers_needed, lead_time_weeks=4+queue_weeks)
        # UNAM capacity reserve
        reserve_workshop(wafers_needed, weeks=3)
        # Packaging order
        order_amkor(wafers_needed, lead_time_weeks=2)

Cost summary:

Per chip:

TSMC wafer share: $40 (1000/25).
UNAM BEOL: $20.
Test: $10.
Packaging: $30.
Logistics: $5.
Margin: $50.
Customer price: ~$155-250.

Experiment: 100K-Chip Production Plan

Target: 100K chips in 2027.

Math:

100K / 25 = 4000 wafers.
4000 wafers / 50 weeks = 80 wafers/week.

Capacity:

UNAM 5 wafers/week → 16× growth needed.
Or 16 parallel workshops (impractical).
Mini-fab needed (chapter 7.5).

Logistics:

TSMC order: 4000 wafers/year = 80 wafers/week within TSMC schedule.
Cost: 4000 × $1000 =$ 4M/year wafer purchase.
Packaging: 4000 × $30 =$ 120K/year. Taiwan contract.

Personnel:

UNAM 14× growth: 14 × 15 = 210 engineers. Too large.
Mini-fab: 50 engineers + 100 technicians. More efficient.

Conclusion: UNAM doesn’t suffice for 100K/year Y1 production. Mini-fab transition mandatory 2027-2028.

Quick Quiz

1/6SIDRA Y1 wafer production timeline?

Lab Exercise

Y1 production-speed analysis.

(a) Single wafer 12 weeks. Daily output via pipeline?

1-2 wafers/day (parallel WIP).

(b) Annual output 7000 chips → cost per chip?

$103 production,$ 250 sale → $150 margin.

Mini-fab $70M + opex$ 20M/year.

(d) Payback time?

100K × $150 margin =$ 15M/year. Mini-fab $70M /$ 15M = 4.7 years.

(e) Feasible for Türkiye?

5-year ROI is fine. Strategic (semiconductor sovereignty) bonus.

Cheat Sheet

3 months/wafer: TSMC + UNAM + test + packaging.
TSMC: 4 weeks CMOS substrate.
UNAM: 3 weeks BEOL memristor.
Test + packaging: 5 weeks.
Output/wafer: 25 ship-ready chips (yield 67%).
Y1 workshop: 7K chips/year.
Y10 mini-fab: 1M chips/year.

Vision: Single-Site Production

Y1: Multi-site (TSMC + UNAM + Taiwan).
Y3: Domestic packaging (Türkiye).
Y10: Mini-fab Türkiye = single site.
Y100: Full fab Türkiye.
Y1000: Wafer-scale, single wafer = single chip.

Prerequisites

What you'll learn here

🪝 Hook: 3 Months from Order to Package

🧭 Intuition: Multi-Site, Single Flow

📐 Formalism: Wafer Flow

🧪 Experiment: 100K-Chip Production Plan

📝 Quick Quiz

🛠️ Lab Exercise

🗂️ Cheat Sheet

🔮 Vision: Single-Site Production

📚 Further Reading