🔌 Module 5 · Chip Hardware · Chapter 5.7 · 10 min read

TIA — Transimpedance Sensing

Microamps to millivolts — the heart of the sense circuit.

Prerequisites

What you'll learn here

  • Explain the TIA (Transimpedance Amplifier) principle and why it's needed
  • Write the op-amp + feedback resistor math ($V_{out} = -I_{in} R_f$)
  • State TIA gain, bandwidth, noise trade-offs
  • Compute Y1 TIA design parameters (R_f, gain, BW)
  • Understand how TIA outputs feed an ADC

Hook: Tiny Currents, Voltage-Hungry ADCs

Crossbar column output: 1-10 µA. Tiny. The ADC (8-bit) typically expects a voltage input in 0-1 V.

Need: convert current to voltage, and amplify.

Solution: TIA (Transimpedance Amplifier). Op-amp + feedback resistor. Linear current-to-voltage; gain range is wide.

In Y1, every crossbar column tail has a TIA. Intermediate stage between crossbar and TDC/ADC.

Intuition: Current-to-Voltage Transformer

The op-amp’s negative input is a virtual ground (ideal op-amp assumption). The feedback resistor RfR_f steers the current through itself instead of to ground:

Vout=−Iin⋅RfV_{out} = -I_{in} \cdot R_f

Gain: transimpedance (V/A). Typical SIDRA: Rf=100R_f = 100 kΩ → 1 µA → 100 mV. The ADC’s preferred range.

Pros:

  • Linear (op-amp).
  • Low input impedance (virtual ground) → doesn’t load the crossbar.
  • Adjustable gain (change RfR_f).

Cons:

  • Op-amp noise (~5-10 nA RMS input-referred).
  • Bandwidth-limited (RfR_f × CparasiticC_{parasitic}).
  • Op-amp draws power.

Formalism: TIA Design

L1 · Başlangıç

Classical TIA:

   I_in (crossbar)
     ↓
─────●───────[Op-amp]── V_out
     │  (-)         
    [R_f]       
     │            
─────┴───●(+)─── V_ref (~0)

Vout=Vref−Iin⋅RfV_{out} = V_{ref} - I_{in} \cdot R_f

In practice Vref=0V_{ref} = 0 → Vout=−IinRfV_{out} = -I_{in} R_f.

Sign flips → either an extra inverter or a different ADC reference keeps polarity right.

Y1 typical:

  • Rf=100R_f = 100 kΩ
  • IinI_{in} range: 100 nA - 10 µA
  • VoutV_{out} range: -10 mV to -1 V

ADC 0-1 V → invert it or use bipolar ADC.

L2 · Tam

Bandwidth:

TIA bandwidth is bounded by op-amp gain × parasitic capacitance:

f−3dB=12πRfCtotf_{-3dB} = \frac{1}{2\pi R_f C_{tot}}
  • CtotC_{tot}: feedback resistor + op-amp input + crossbar parasitic, ~1 pF.
  • Rf=100R_f = 100 kΩ → f−3dB=1.6f_{-3dB} = 1.6 MHz.

MVM 67M/s → 15 ns each. Enough bandwidth? Settling time ≈ 5τ=5/(2πf−3dB)=5005 \tau = 5/(2\pi f_{-3dB}) = 500 ns. Way too slow!

Fix: smaller RfR_f (10 kΩ) → bandwidth 16 MHz, settling 50 ns. Still slow.

In practice: TIA bandwidth caps Y1’s MVM rate. Many TIAs in parallel (one per column) + time-shared.

Noise:

Op-amp noise density ~5 nV/Hz5 \text{ nV}/\sqrt{Hz}. Total noise: σV=5 nV⋅f−3dB=5 nV⋅16×106=20\sigma_V = 5 \text{ nV} \cdot \sqrt{f_{-3dB}} = 5 \text{ nV} \cdot \sqrt{16 \times 10^6} = 20 µV. In current: σI=σV/Rf=20\sigma_I = \sigma_V / R_f = 20 µV / 10 kΩ = 2 nA. Very low → great SNR.

Main noise: resistor thermal 4kTRfΔf4 k T R_f \Delta f. σI2=4kTΔf/Rf=4⋅1.38×10−23⋅300⋅16×106/104=2.6×10−17\sigma_I^2 = 4 k T \Delta f / R_f = 4 \cdot 1.38 \times 10^{-23} \cdot 300 \cdot 16 \times 10^6 / 10^4 = 2.6 \times 10^{-17} σI=5.1\sigma_I = 5.1 nA. Same order as op-amp.

Total: σI=22+52≈5.4\sigma_I = \sqrt{2^2 + 5^2} \approx 5.4 nA. Vs a 1 µA signal, SNR ~200 → 23 dB. Sufficient but improvable.

L3 · Derin

Auto-zeroing:

Op-amp DC offset (~mV) shifts the output. Auto-zero technique: zero the TIA before each measurement, remember the offset, subtract at the output.

Steps:

  1. Phase 1: I_in = 0, measure V_out = V_offset, store.
  2. Phase 2: connect crossbar, true V_out = V_total - V_offset.

DC offset gone → precision rises.

Cascode + folded cascode:

For high gain, 2-stage op-amp. SIDRA Y1: folded cascode → 80 dB DC gain, 10 MHz bandwidth. Practical.

Variable gain:

RfR_f programmable (with switching transistors). Low current → high RfR_f (high gain). High current → low RfR_f (large dynamic range).

Y10 hybrid approach:

Classical TIA + TDC: TIA voltage feeds an integrator, the TDC times the result. Two stages → both precision and speed.

Alternative: TIA-free TDC:

Charge the TDC capacitor directly with crossbar current. Skip the TIA. Simpler but no gain control.

In Y10, most cases use TIA-free TDC; special cases keep the TIA.

Experiment: Convert 5 µA to 500 mV

Settings: Rf=100R_f = 100 kΩ. Iin=5I_{in} = 5 µA.

Vout=−IinRf=−5×10−6⋅105=−0.5V_{out} = -I_{in} R_f = -5 \times 10^{-6} \cdot 10^5 = -0.5 V = -500 mV.

(Add an inverter for positive sign: Vout=+500V_{out} = +500 mV.)

ADC (8-bit, 0-1 V): 500 mV / 1 V × 256 = 128 (mid-range).

Correct: the original 5 µA = 50% of the 1-10 µA dynamic range. 128/256 = 50%. Consistent.

Latency:

  • TIA settling: 50 ns (with Rf=10R_f = 10 kΩ).
  • ADC: 5 ns.
  • Total: 55 ns/column.

256 columns parallel TIA + ADC → all columns read in 55 ns. MVM time (TIA included) ~70 ns.

Quick Quiz

1/6What does a TIA do?

Lab Exercise

Y1 TIA design optimization: dynamic range vs speed.

Goal: 100 nA - 10 µA range (100× dynamic), MVM in 50 ns.

Settings:

  • Fixed RfR_f design: single value.
  • Variable RfR_f design: 1 MΩ at low current, 10 kΩ at high current.

Questions:

(a) Fixed Rf=100R_f = 100 kΩ with 10 µA output: what V? (b) Same R_f at 100 nA: what V? Precision? (c) Variable R_f logic: which R_f at which current? (d) Settling time in both cases? (e) Which design is right for Y1?

Solutions

(a) Vout=10µA×100kΩ=1VV_{out} = 10 µA × 100 kΩ = 1 V. Hits ADC top.

(b) Vout=100nA×100kΩ=10mVV_{out} = 100 nA × 100 kΩ = 10 mV. Only 2-3 LSBs of an 8-bit ADC → very coarse.

(c) Variable: I < 1 µA → R_f = 1 MΩ; I > 1 µA → R_f = 10 kΩ. Add a switch.

(d) Fixed R_f = 100 kΩ → 50 ns settling. Variable: 1 MΩ → 500 ns; 10 kΩ → 5 ns. Asymmetric.

(e) Fixed R_f is simple but limits dynamic range. Variable wins for Y1: two R_f levels with a switch = fast, sensitive, modest complexity. Y3+ moves to 4-8 levels.

Cheat Sheet

  • TIA: current → voltage. V=−IRfV = -I R_f.
  • Op-amp + feedback resistor. Linear, virtual ground.
  • Gain: set by RfR_f.
  • Bandwidth: 1/(2πRfC)1/(2\pi R_f C), settling 5 RC.
  • Noise: thermal + op-amp ~5 nA RMS.
  • Y1: TIA + ADC per column. Y10: mostly TIA-free TDC.
  • Auto-zero: removes DC offset.
  • Variable gain: widen dynamic range.

Vision: Direct Current Sensing Replaces TIA

TIA is a classical analog circuit. New-generation sense circuits read current/charge directly:

  • Y1: TIA + ADC (classical).
  • Y3: TIA + TDC hybrid (less area).
  • Y10: TIA-free TDC standard.
  • Y100: Single-photon precision (photonic).
  • Y1000: Spike-based, TIA unnecessary.

For Türkiye: TIA design is core analog circuit skill. Y1’s TIA design is competitive thanks to the academic engineering tradition.

Further Reading

  • Next chapter: 5.8 — MUX, Decoder, and Analog ECC
  • Previous: 5.6 — TDC: Time-Domain Readout
  • TIA classic: Razavi, Design of Analog CMOS Integrated Circuits, Ch. 9.
  • Auto-zero: Enz & Temes, Circuit techniques for reducing the effects of op-amp imperfections, Proc. IEEE 1996.
  • Memristor sense: Hu et al., Memristor crossbar-based neuromorphic computing system, IEEE TNNLS 2014.